I am trying to upgrade ccsv3.2 to ccvv5 and have had many problems. The latest is this.
I get these errors when building:
>>>>>
error #10056: symbol "_MDIO_timerTick" redefined: first defined in
.../Src/TiLteLib/cixcvrProductEC/LTE/lib/csl_3x_C6482_v3_00_10_01/csl_c6482.lib<csl_mdio.o>";
redefined in
.../Src/Ti/ndk/lib/hal/dsk6455/hal_eth_c6455.lib<c6455_mdio.o64P>"
and about 8 more MDIO related errors.
>>>
How do I fix this problem?? I need both of these libraries.
I see one issue.
I have an old map file form the ccv3.2
These are the largest sections from the hal_eth library
ccv3.2:
size
000001dc hal_eth_c6455.lib : llpacket.o64P (.far)
ccv5
00001620 hal_eth_c6455.lib : ethdriver.o64P (.far)
Bryan,
I think you were using a different version of the NDK with your CCS 3.2 setup, vs. in your CCSv5 setup, is that true?
Bryan Hehn000001dc hal_eth_c6455.lib : llpacket.o64P (.far)
This is the "old" driver design called "LL architecture". It's been replaced by NIMU architecture in newer NDK and NSPs.
Bryan Hehn00001620 hal_eth_c6455.lib : ethdriver.o64P (.far)
This one is probably using the newer NIMU design.
So I think that explains this difference you are seeing.
Steve
These errors are indicating that your IRAM memory segment is all used up. You should try placing some of these sections shown in the error messages (e.g. .trace) into different memory segments. You can do this using the BIOS config tool.
Please check out this post since it's almost exactly the same issue:
http://e2e.ti.com/support/embedded/bios/f/355/p/184869/667442.aspx#667442
I don't have SARAM and DARAM defined.
I am using the TCI6482 Eval Module. My memory map puts everything into IRAM. There is external ram (DDR2) . What are some sections I could map into DDR2?
By the way – this is a legacy project that I did not create. I’m just trying to port it to ccv5.
You can start by placing the sections that you are seeing in the error messages into DDR2, in order to get everything building.
However, DDR2 is external memory and hence it is slower than IRAM. So, you may want to consider making some optimizations by placing/swapping sections that need faster access times from external DDR2 into internal IRAM.