Hi,
I have some problems by integration of the PSP " BIOS PSP DM8148 03.10.01.00" Feb 09, 2012
I was able to integrate the PSP in my project and the uart example is also working as long I am not switching on the cache
Cache.configureCache = true;
Cache.enableCache = true;
If I switch on the cache then I am getting this error.
[Cortex_M3_RTOS] Uart is configured in polled modeti.sysbios.family.arm.m3.Hwi: line 818: E_hardFault: FORCED
[Cortex_M3_RTOS] ti.sysbios.family.arm.m3.Hwi: line 895: E_busFault: IMPRECISERR
[Cortex_M3_RTOS] Exception occurred in background thread.
[Cortex_M3_RTOS] Exception occurred in ThreadType_Main.
[Cortex_M3_RTOS] Main handle: 0x0.
[Cortex_M3_RTOS] Main stack base: 0x81000000.
[Cortex_M3_RTOS] Main stack size: 0x10000.
[Cortex_M3_RTOS] R0 = 0x00060001 R8 = 0x00000000
[Cortex_M3_RTOS] R1 = 0x48140000 R9 = 0x00000000
[Cortex_M3_RTOS] R2 = 0x00000000 R10 = 0x00000000
[Cortex_M3_RTOS] R3 = 0xfffffff1 R11 = 0x00000000
[Cortex_M3_RTOS] R4 = 0x00000000 R12 = 0x820315e8
[Cortex_M3_RTOS] R5 = 0x00000000 SP(R13) = 0x8100ffa8
[Cortex_M3_RTOS] R6 = 0x00000000 LR(R14) = 0x8204715d
[Cortex_M3_RTOS] R7 = 0x81010000 PC(R15) = 0x82047164
[Cortex_M3_RTOS] PSR = 0x41000000
[Cortex_M3_RTOS] ICSR = 0x00400803
[Cortex_M3_RTOS] MMFSR = 0x00
[Cortex_M3_RTOS] BFSR = 0x04
[Cortex_M3_RTOS] UFSR = 0x0000
[Cortex_M3_RTOS] HFSR = 0x40000000
[Cortex_M3_RTOS] DFSR = 0x00000000
[Cortex_M3_RTOS] MMAR = 0xe000ed34
[Cortex_M3_RTOS] BFAR = 0xe000ed38
[Cortex_M3_RTOS] AFSR = 0x00000000
[Cortex_M3_RTOS] Terminating execution...
BR
Mesut
Hi Mesut,
If you refer section 3 of the DM8148_BIOSPSP_ReleaseNotes(placed in top level docs folder), CPU drivers support is only provided for ARM A8 core. M3 core support is not provided.
For enabling cache on M3 core, you will have to configure the AMMU and cache appropriately. Otherwise you will get such exceptions. In case if you need this, you will have to wait for the next upcoming release.
Best Regards,
Raghavendra
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