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DM368 IPNC MMC1 clock issue

bibin b ponattil
Prodigy 165 points

Hi all,

We are working on a product based on dm368 IPNC RDK 5.1. We have a requirement of using MMC1 to interface WiFi Module(WL1273) as SDIO interface

Wifi Module is working fine on MMC/SD1 when we configured pll's at a lower clock rates which is suggested for DM365. The Function clock for MMC/SD1 conntoller was 135 MHz and eventhough 135 MHz exceeds the maximum frequency limit of 100MHz(as specified in SPRUFH5B - MMC/SD controller userguide) module worked fine. But when we configured pll's for higher clock rate suggested for DM368, Wifi module is not working at all eventhough we tried function clock frequencies of 97MHz,106MHz,112MHZ,136MHz, and 170 MHz.

MMC/SD1 functional clock is generated from PLL1SYSCLK4 which itself is used for Config Bus, Peripheral System Interfaces, EDMA etc. So we have many constraints in adjusting the functional clock. Any suggestion to configure MMC/SD1 of DM368 are welcome
Please help on this. This is very urgent for us.

  • 0
    TI__Expert 7225 points

    HI All,

    More info here from customer:

    Our board is also based on IPNC ref design from Appro. We are using IPNC RDK 5.1 and ported for our board. As per your reference schematics wifi module is GT86722B but we are using wl1273. But reference code in IPNC RDK 5.1 is configured for wl12xx. As shown in your reference schematics our wifi module is also interfaced via mmc1 sdio.

    We are reusing the PLL1/PLL2 settings in reference SDK.

    Please see the clock frequencies which we are using as follows:

    DM368 running in 297 MHZ(Low frequency configuration with which wifi is working)
    ------------------------------------------------------------------------------------------------------------------------


    ARM PLL2SYSCLK2 -> 297MHZ

    DDR PLL1SYSCLK7 -> 270MHZ

    USB PHY PLL1SYSCLK1 -> 24.54MHZ
    MJCP/HDVICP PLL1SYSCLK3 -> 270MHZ
    EDMA/Peripheral/MMC1 PLL1SYSCLK4 -> 135MHZ  >>>>>mmc1 controller>>20MHZ>>>wl1273 wifi module(working fine)
    VPSS PLL1SYSCLK5 -> 270MHZ
    MMC0/SD0 PLL1SYSCLK8 -> 135MHZ

    DM368 running in 432 MHZ(High frequency configuration with which wifi is not working)
    ------------------------------------------------------------------------------------------------------------------------

    ARM PLL2SYSCLK2 -> 432MHZ

    DDR PLL1SYSCLK7 -> 680MHZ

    USB PHY PLL1SYSCLK1 -> 24.3MHZ
    MJCP/HDVICP PLL1SYSCLK3 -> 340MHZ
    EDMA/Peripheral/MMC1 PLL1SYSCLK4 -> 170MHZ  >>>>>mmc1 controller>>20MHZ>>>wl1273 wifi module(card not detected)
    VPSS PLL1SYSCLK5 -> 360MHZ
    MMC0/SD0 PLL1SYSCLK8 -> 48MHZ

    We tried to reduce EDMA/Peripheral/MMC1 PLL1SYSCLK4 -> 170MHZ to EDMA/Peripheral/MMC1 PLL1SYSCLK4 -> 135/113MHZ and wifi card detected but sdio write failed.

    Could you please suggest proper settings/clk ratio for EDMA/Peripheral/MMC1 PLL1SYSCLK4 for the proper working of wifi module with ARM clock 432 MHZ?

    Best Regards

    Feroz

  • 0
    Prodigy 10 points

    Please visit www.dm36x.com

  • 0 in reply to K Md Feroz Irfan
    Intellectual 780 points

     

    We have a similar problem: we are trying to use an SDIO WiFi module with our DM368 chip. It seems to work with MMC0 but not with MMC1.

    Setting the clocks to match DM365 did not help.

    The WiFi module is detected, but we get CRC errors which make it unusable.

  • 0 in reply to Gadi Bergman
    Intellectual 780 points
    Our problem is now solved by disabling the pulldown bits to the DATA lines.
    In file /arch/arm/mach-davinci/devices.c changed:
    __raw_writel((__raw_readl(pupdctl1) & ~0x400),
    pupdctl1);
    to:
    __raw_writel((__raw_readl(pupdctl1) & ~0xFC0),
    pupdctl1);