I am trying to write a kernel module that will handle multiple different MSI interrupts generated from a single EP. During boot I see this:
[ 16.741897] keystone-pcie: pcie - number of legacy irqs = 4
[ 16.741940] keystone-pcie: pcie - number of MSI host irqs = 8, msi_irqs = 32
I do not necessarily need 32 MSI irqs but why does it show MSI host irqs = 8?
In my kernel module, I call pci_enable_msi_block(dev, 32) and it returns 4 to me. I assume this means that I should then call pci_enable_msi_block(dev, 4) in order to enable 4 MSI interrupts, unfortunately this call returns 1. Which I assume means that the device can only enable 1 MSI interrupts (why would it return 4 before?). I then call pci_enable_block(dev, 1) and sucesfully enable 1 MSI. How do I go about enabling more MSI? Am I correct that since I am enabling host side interrupts, it should not matter how many MSI are enabled on the EP?
lspci -v before the kernel module is inserted:
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at <ignored> (32-bit, non-prefetchable)
Memory at <ignored> (32-bit, prefetchable)
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00001000-00001fff
Memory behind bridge: 50000000-501fffff
Prefetchable memory behind bridge: 50200000-503fffff
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: pcieport
01:00.0 Memory controller: Xilinx Corporation Device 7022
Subsystem: Xilinx Corporation Device 0007
Flags: fast devsel
Memory at 50000000 (32-bit, non-prefetchable) [disabled] [size=1M]
Capabilities: [80] Power Management version 3
Capabilities: [90] MSI: Enable- Count=1/4 Maskable- 64bit+
Capabilities: [c0] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
lspci -v after kernel module is inserted:
00:00.0 PCI bridge: Texas Instruments Device 8888 (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0
Memory at <ignored> (32-bit, non-prefetchable)
Memory at <ignored> (32-bit, prefetchable)
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00001000-00001fff
Memory behind bridge: 50000000-501fffff
Prefetchable memory behind bridge: 50200000-503fffff
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: pcieport
01:00.0 Memory controller: Xilinx Corporation Device 7022
Subsystem: Xilinx Corporation Device 0007
Flags: bus master, fast devsel, latency 0, IRQ 576
Memory at 50000000 (32-bit, non-prefetchable) [size=1M]
Capabilities: [80] Power Management version 3
Capabilities: [90] MSI: Enable+ Count=4/4 Maskable- 64bit+
Capabilities: [c0] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Kernel driver in use: Custom_Module
Any help would be appreciated, this is kind of putting development at a standstill due to our need for multiple MSI interrupts. I have also attatched the relevent code from my kernel module if that is needed.