• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 398 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM365 hang sending H.264 over ethernet

Pete Eberlein
Intellectual 580 points

Using Linux kernel 2.6.37
DVSDK 4_02_00_06
H.264 encoder version 02.30.00.06

The problem is that after a few minutes of sending H.264 encoded video over ethernet, the Linux kernel will hang and nothing will be output on the serial port or respond to network.

I have followed the Stop-mode instructions for debugging the Linux kernel in Code Composer 5, and I can stop the CPU and see the address and function being executed.  It seems that the kernel is stuck doing asm_do_IRQ with irq set to 0 or 16.  When irq==0, the handler function is vpfe_isr in vpfe_capture.c.  When irq==16, the handler function is dma_irq_handler in dma.c.  I let the debugger run and pause it repeatedly and I've only seen it stop in the asm_do_IRQ with irq 0 or 16, leading me to believe that the CPU is handling IRQs and doing nothing else.  Maybe an IRQ is not getting cleared, so it triggers again immediately?

Has anyone seen this before, or have any suggestions on how to fix it?

  • 0
    Intellectual 580 points

    I've attempted a tentative fix for this problem, tested for a couple hours now, and the kernel hasn't hung yet.  Here's a patch (tabs may be mangled)

    This patch fixes the case where there may be a DMA channel pending on bank 0 and bank 1 simultaneously, and the channel on bank 1 would not be cleared since it was clearing only one bank.

     

    --- linux/arch/arm/mach-davinci/dma.c    (revision 35020)
    +++ linux/arch/arm/mach-davinci/dma.c    (working copy)
    @@ -396,6 +396,11 @@
                         channel, DMA_COMPLETE,
                         edma_cc[ctlr]->intr_data[channel].data);
             }
    +        if (!sh_ipr && bank == 0) {
    +            sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
    +            sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
    +            bank = 1;
    +        }
         } while (sh_ipr);
         
         edma_shadow0_write(ctlr, SH_IEVAL, 1);