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BBB based custom board SPI NOR boot query

Hi ,

We are using BBB(am335x) based custom board.
Boot device for board is SPI NOR flash i.e. SPL resides in the SPI NOR flash.
We had created four partitions in the SPI NOR flash (128k bytes each) and we were expecting that if first partition doesn't contain the valid SPL copy then ROM code would try next partition as it does for NAND Flash.

But during experiment we found that ROM code actually doesn't go to next partition.

While referring TRM of AM335x we found that ROM Code checks 4 sectors(1 sector = 512 bytes) for valid SPL.
(TRM section : 26.1.7.6.3 SPI Read Sector Procedure).
BUt another section of the TRM says for SPI NOr also ROM code checks 4 blocks.
(TRM section : 26.1.7.7 Blocks and Sectors Search Summary).

Now i have following question regarding this.
1. If ROM code checks 4 blocks for SPI NOR flash, what is the size of the block. Is block size equal to sector size(512 bytes)
2. Is there any way to maintain multiple copies of SPL in SPI NOR and ROM code goes checking all the copies of SPL in SPI NOR before going to Next device?


Thank you,

Regards,
Ankur

  • Hi Ankur,

    What is the sector size of your NOR flash ?

    What is your size of SPL binary ? check whether it fits into single sector of your flash.

    As we know, NAND flash is formed with blocks and NOR is formed with sectors.

    Ex:

    NAND -> Die -> 1024 block ->  1 block (128KiB) = 64 pages -> page size = 2KiB or 4KiB

    NOR -> Die -> 32 sectors ->  1 sector (64KiB) = 256 pages -> page size = 256Bytes

    http://www.micron.com/-/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/M25P/M25P16.pdf.

    Please refer to your SPI NOR flash data sheet.

  • Hi Titus,

    Sector size of NOR flash(M25PE80) is 64KiB and page size is 256 bytes as you have rightly mentioned.

    Main confusion is how ROM code sees the SPI boot devices, because in TRM there two sections,

    26.1.7.6.3 SPI Read Sector Procedure
    The ROM Code reads SPI data from the boot device in 512 byte sectors. For each call to the SPI Read
    Sector routine, the SPI Read Command (0x03) is sent along with the 24 bit start address of the data to be
    read. Each Sector = 512bytes and the ROM bootloader will attempt the following:
    1. Read Sector 1, Check the address: 0x0
    2. Read Sector 2, Check the address: 0x200
    3. Read Sector 3, Check the address: 0x400
    4. Read Sector 4, Check the address: 0x600

    and another section says

    26.1.7.7 Blocks and Sectors Search Summary
    Table 26-31 summarizes numbers of blocks and sectors which are searched during the memory booting
    from devices requiring image shadowing. NAND is organized with blocks, which are erasable units.

    So now doubt ariases what ROM code follows ? if it is 4 blocks for or 4 sector in case of SPI devices ?
    Those sections are source of misunderstanding.

    Thank you,

    Regards,
    Ankur

  • Hi Ankur,

    What is your size of SPL binary ?

    In my understanding,

    Table 26-31 is for NON-XIP memory models and not for NOR flash (sector based) so it could search only first 4 sectors of flash for valid SPL image.

  • Hi Titus,

    Thank you for reply,


    size of our SPL binary is around 64k. 25k. [corrected the spl size]

    Table is for NON-XIP based memory model, it also includes SPI which means SPI EEPROM & SPI NOR, right?
    I just want to get idea about how ROM code checks SPI NOR flash, if it is based on the SPI NOR architecture or its uniform across the architecture?

    Based on that we have to see how we can keep 4 redundant copies of the SPL in SPI NOR flash.
    Do you have any suggestions for that ?

    Thank you,

    Regards,
    Ankur

  • Ankur
    I assume you have seen the below in the TRM. I wonder if this is what you are asking for? I guess what can be done is have a small boot loader in the first sector and then get the real code from another part of the SPI flash. I hope this helps.


    26.1.7.6.3 SPI Read Sector Procedure
    The ROM Code reads SPI data from the boot device in 512 byte sectors. For each call to the SPI Read
    Sector routine, the SPI Read Command (0x03) is sent along with the 24 bit start address of the data to be
    read. Each Sector = 512bytes and the ROM bootloader will attempt the following:
    1. Read Sector 1, Check the address: 0x0
    2. Read Sector 2, Check the address: 0x200
    3. Read Sector 3, Check the address: 0x400
    4. Read Sector 4, Check the address: 0x600

    Regards
    Mohsen