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Mutiple SPIs transmission on DM368

I am using  DM368 EVM board, DVSDK4.02, kernel 2.6.32, three SPIs work on DM368.

1、SPI0(master mode): DM368 send image data to FPGA through SPI0+EDMA,and channel of the EDMA  is 16;

2、SPI1(slave mode): DM368 receive data packet  from FPGA, the data packet is for changing bitrate of image data, SPI1 receiving by interrupt, and the                       interrupt   number is 18;

3、SPI2(master mode): DM368 send data packet to FPGA when DM368 have changed bitrate, the send packet data is same to the receive data packet.

the three SPI work normally when they are loaded separately, and  in general the three SPI work normally when they are all loaded. when they are all loaded, SPI0  loaded first, SPI1  loaded  second, SPI2  loaded last.

my problem: in the case of the three SPIs loaded all,  the SPI1 can't receive  data packet  from FPGA  sometime when the DM368 power up, and i known FPAG has sended data packet through the oscilloscope.

I think there may be some conflit betwen EDMA of  the  SPI0and  interrupt of the SPI1?

SOS

thanks!