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EVMK2H CCSv6 / XDS200 cannot connect to DSP cores after Linux boot

Bernard Oliver
Expert 1020 points

Hi,

I boot Linux on my EVMK2H, and then attempt, using CCSv6 through XDS200, to run a simple app. such as helloworld, on any of the DSP cores.

I get the following message: Error connecting to the target: (Error -1180 @ 0x0). Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 5.1.641.0)

I have checked the cores using mpmcl and they are OK, and I can run compiled code on them.

I have also tried setting the Linux environmental variable debug_options to 1, to no avail. Also have reduced XDS clock speed. All is  Vanity futility.

Help. How do I take the core (?) out of reset?

Thanks,

Bernard

  • 0
    TI__Mastermind 29520 points
    Hello Bernard,

    Please take a look on a similar issue in e2e forum - e2e.ti.com/.../1204753
    e2e.ti.com/.../1274052

    Do you use gel files for your board?

    Best regards,
    Yanko
  • 0 in reply to Yanko Todorov-XID
    TI__Mastermind 29520 points
    Bernard,

    CCSv6 does support the XDS200 emulator. When choosing the connection, just select the Texas Instruments XDS2xx USB Debug Probe.

    Your problem might be caused by XDS 200 driver.
    Take a look on following wikies:
    processors.wiki.ti.com/.../Updating_CCSv6

    processors.wiki.ti.com/.../Device_Specific_Workshops_with_CCS

    See the workaround described in this thread:
    e2e.ti.com/.../390961

    Based on this information you must update your CCS6 drivers.

    Best regards,
    Yanko
  • 0
    TI__Guru** 116100 points
    Hi Bernard,

    Have you set boot mode setting to "DSP no-boot mode" ?

    SW1 "0.0.0.1" (P1.P2.P3.P4)
  • 0 in reply to Titusrathinaraj Stalin
    Expert 1020 points

    Hi Titus,

    I updated the XDS200 to latest version as per links you guys provided.
    I cannot debug ARM or DSP cores using CCSv6 n either no boot mode, or after Linux has booted, as per test results below.
    Prior to each attempt, I ran the .ccxml "Test Connection" and got: "The JTAG DR Integrity scan-test has succeeded."

    The test results are:
    --------------------------------------------------
    1. Linux boot (SW1: 0010)
    1.1 Debug helloworld.c on DSP core using CCSv6
    C66xx_0: Error connecting to the target: (Error -1180 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 5.1.641.0)

    1.2. Debug helloworld.c on ARM core using CCSv6
    arm_A15_0: GEL Output:
    Connecting Target...
    arm_A15_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x02620020
    at (*((unsigned int *) 0x02620020)&0x0000000E) [xtcievmk2x.gel:518]
    at OnTargetConnect()
    arm_A15_0: File Loader: Verification failed: Values at address 0x000000000C000000 do not match Please verify target memory and memory map.
    arm_A15_0: GEL: File: /home/bernard/workspace_66ak2h/helloArm/Debug/helloArm.out: a data verification error occurred, file load failed.
    arm_A15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4

    -------------------------------------------------------
    2. no boot mode (SW1: 0001)
    2.1 Debug helloworld.c on DSP core using CCSv6
    C66xx_0: GEL Output:
    Connecting Target...
    C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.4
    C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000
    C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040
    C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048
    C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048
    C66xx_0: GEL Output: (2d) Delay...
    C66xx_0: GEL Output: (2e) SECCTL = 0x00810000
    C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A
    C66xx_0: GEL Output: (2g) Delay...
    C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048
    C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
    C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000
    C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
    C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
    C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
    C66xx_0: GEL Output: (7) SECCTL = 0x00890000
    C66xx_0: GEL Output: (8a) Delay...
    C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
    C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
    C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
    C66xx_0: GEL Output: (8d/e) Delay...
    C66xx_0: GEL Output: (10) Delay...
    C66xx_0: GEL Output: (12) Delay...
    C66xx_0: GEL Output: (13) SECCTL = 0x00090000
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
    C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
    C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
    C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27!
    etc, etc

    2.2 Debug helloworld.c on ARM core using CCSv6
    arm_A15_0: GEL Output:
    Connecting Target...
    arm_A15_0: GEL Output: TCI6638K2K GEL file Ver is 1.3
    arm_A15_0: GEL: Error while executing OnTargetConnect(): identifier not found: DNUM
    at (DNUM==0) [xtcievmk2x.gel:593]
    at Global_Default_Setup_Silent() [xtcievmk2x.gel:528]
    at OnTargetConnect()
    arm_A15_1: Error connecting to the target: (Error -6305) PRSC module failed to write to a router register. (Emulation package 5.1.641.0)

    I did follow the example in MCSDK UG and loaded and ran Linux kernel using tftp with initrd (and set args_ramfs to 10M to fit the image) Could this have done something. But surely it wouldn't have any effect in the no boot mode??  (args_rams is currently set to the original 9M)

    Best Regards,

    Bernard

  • 0 in reply to Bernard Oliver
    TI__Mastermind 29520 points
    Hello Bernard,

    Could you point us what is the version of your gel files?

    Please take a look on this thread - e2e.ti.com/.../729021
    Try to enable ICEPICK module.

    Best regards,
    Yanko
  • 0 in reply to Yanko Todorov-XID
    Expert 1020 points

    Hi Yanko,

    I am using using xtcievmk2x.gel Ver 1.4

    I have worked through the links, but haven't found a way to enable icepick module . 

    When EVM is in no-boot mode with ARM debug of helloworld.c, I get:

     

     

     

     

     

    When EVM is in no-boot mode with DSP debug of helloworld.c , I get :

    After booting Linux, and with a DSP core debug of helloworld.c , Target Status window is blank with the following Console report:

    C66xx_0: Error connecting to the target: (Error -1180 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 5.1.641.0) 

     

  • 0 in reply to Bernard Oliver
    Expert 1020 points

    Can't paste the screen shot. When I debug using DSP core 0, after I cancel due to timeouts (C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30!)

    Target Status reports:

    IcePick_D_0:   GP

    subpath_1:    CLK On, Power On, CLK Down Inactive, Power Down Inactive, Not in Reset, Reset (None)

    C66xx_0:      LE

    Regards,

    Bernard

  • 0 in reply to Bernard Oliver
    Expert 1020 points
    Hi TI Gurus,

    After 4 weeks I still can't get my new evmk2h to do the most basic stuff.
    CCSv6 cannot debug the DSP core either in a) linux booty, or b) no boot modes.
    Here are the details....

    I have the latest CCSv6
    Linux boots and works. I can execute code on the DSP cores using mpmcl.
    I have updated the XDS200 to latest version (v10006)
    I am using using xtcievmk2x.gel Ver 1.4

    TEST 1
    I create a helloworld project, add a .ccxml with xtcievmk2x.gel
    Mode: no boot
    I debug it and get timeouts...................

    C66xx_0: GEL Output:
    Connecting Target...
    C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.4
    C66xx_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000
    C66xx_0: GEL Output: (3a) PLLCTL = 0x00000040
    C66xx_0: GEL Output: (3b) PLLCTL = 0x00000040
    C66xx_0: GEL Output: (3c) Delay...
    C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
    C66xx_0: GEL Output: MAINPLLCTL0 = 0x07000000
    C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
    C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
    C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
    C66xx_0: GEL Output: (7) SECCTL = 0x00090000
    C66xx_0: GEL Output: (8a) Delay...
    C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
    C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
    C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
    C66xx_0: GEL Output: (8d/e) Delay...
    C66xx_0: GEL Output: (10) Delay...
    C66xx_0: GEL Output: (12) Delay...
    C66xx_0: GEL Output: (13) SECCTL = 0x00090000
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
    C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
    C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
    C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=28!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=29!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=31!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=32!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=33!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=21, md=34!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=35!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=36!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=37!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=38!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=39!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=40!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=41!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=42!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=43!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=44!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=45!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=46!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=26, md=47!
    C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=27, md=48!
    C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
    C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
    C66xx_0: GEL Output: Completed PA PLL Setup
    C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x07080400
    C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040
    C66xx_0: GEL Output: DDR begin
    C66xx_0: GEL Output: XMC setup complete.
    C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
    C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
    C66xx_0: GEL Output: DDR3A initialization complete
    C66xx_0: GEL Output: DDR3 PLL Setup ...
    C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.
    C66xx_0: GEL Output: DDR3B initialization complete
    C66xx_0: GEL Output: DDR done

    IceP:ick appears to work. The first 3 lines in Target Status page report are: (I can't to paste image)
    IcePick_D_0: GP
    subpath_1: CLK On, Power On, CLK Down Inactive, Power Down Inactive, Not in Reset, Reset (None)
    C66xx_0: LE


    TEST 2

    Mode: Linux boot
    Linux boots OK
    I create a helloworld project, add a .ccxml (makes no difference if has or hasn't a .gel), I get:

    C66xx_0: Error connecting to the target: (Error -1180 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 5.1.641.0)

    Best Regards,
    Bernard
  • 0 in reply to Bernard Oliver
    TI__Guru** 116100 points

    Hi Bernard,

    I'm able to connect K2HK EVM board with CCSv6.

    I'm not seeing any issues.

    Able to debug any DSP app on core0 with any other CCS versions ?

    Please make sure that you set the boot mode to "DSP no-boot mode" while debugging.

  • 0 in reply to Bernard Oliver
    TI__Mastermind 18260 points

    Hi Bernard,

    The DSP loader program, mpmcl, utilizes many Linux services to load the program to the DSP.  You typically can't simply load a DSP executable using CCS under the Linux environment.

    One key activity of mpmcl is to take the DSP out of reset.  CCS can't connect to the DSP until it has been taken out of reset.  There may be A15-based GEL files that can do this, but there's more to running the DSP than just taking it out of reset, and you would need GEL support for those as well.

    If you need to debug the DSP using CCS while Linux runs on the ARM then the recommended procedure is:

    1. Put a spin loop in your DSP program main() function, based on a variable that you will change through CCS:
      int spin = 1;
      int main(int argc, char *argv[])
      {
          while (spin);
          ...
      }
    2. Load and start the program as you would normally through mpmcl
    3. Connect CCS to DSP
    4. Set any breakpoints you might need
    5. Change global var 'spin' to 0
    6. Run DSP (which will now proceed past the spin loop)

    Regards,

    - Rob

     

  • 0 in reply to Robert Tivy
    TI__Mastermind 18260 points

    Robert Tivy said:
    1. Put a spin loop in your DSP program main() function, based on a variable that you will change through CCS:
      int spin = 1;
      int main(int argc, char *argv[])
      {
          while (spin);
          ...
      }
    2. Load and start the program as you would normally through mpmcl
    3. Connect CCS to DSP
    4. Set any breakpoints you might need
    5. Change global var 'spin' to 0
    6. Run DSP (which will now proceed past the spin loop)

    Forgot to mention step 3a:
         3a. Load DSP program's symbols into CCS

    Regards,

    - Rob

  • 0 in reply to Robert Tivy
    Expert 1020 points

    Robert.

    Thank you. It's all clear now
    Regards,
    Bernard
  • 0
    TI__Guru 50170 points

    Hi, Bernard,

    The bottom line of your issue is that DSP cores are not powered up by u-boot. You need to set the u-boot environment variable, debug_options, to take DSP cores out of reset. Please see the link for more details.

    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Why_can.27t_I_connect_to_DSP_cores_from_CCS_in_latest_u-boot.3F

    Rex