Hi,
I have connected a SPI slave on SPI0 of Am335x EVM.
Slave is in SPI_MODE_1, sends 24-bit per word
For testing the functionality of slave device, I am configuring McSPI within slave device driver hence not using omap mcspi driver (spi0 is disabled in am335x-evm.dts)
This is the register configuration that I am doing in device driver :
void __iomem *spi_addr = ioremap_nocache(0x48030000, 0x400); void __iomem *clock_addr = ioremap_nocache(0x44e00000, 0x400); // enable SPI0 module clock iowrite32(0x2, clock_addr+0x4c); //SPI SYSCONFIG //smart idle mode, automatic OCP clock gating iowrite32(0x11, spi_addr+0x110); //SPI MODULCTRL // single channel iowrite32(0x1, spi_addr+0x128); //SPI CH0CONF //PHA = 1, CLKD = 0x4, WL = 0x17, TRM = 1 iowrite32(0x40b91, spi_addr+0x12c); //SPI CH0CTRL //channel0 active iowrite32(0x1, spi_addr+0x134);
Since FIFO is disabled for Rx, when I enable the channel 0, will SPI_RX0 register (offset 0x13c) contain the data received from slave ?
Description of SPI_RX0 register says - "The McSPI channel 0 FIFO receive buffer register (MCSPI_RX0)"
Since i am not using FIFO for Rx, will this register still contain the data received from slave ? If no, then which register shall I read.
thanks