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CPTS PTP Implementation

Hi,

I am using Vayu EVM and I implemented PTP application to get HW Timestamp of Packets reaching HW.

I configures the CPTS to get the timestamp. I get the proper timestamp for sometime after which I get the following error thrown.

This is continuously printed even after i terminate my application untill I restart the board!!

[ 3022.757904] cpts: event pool is empty
[ 3022.761749] cpts: unable to obtain a time stamp
[ 3030.789154] cpts: event pool is empty
[ 3030.793029] cpts: unable to obtain a time stamp
[ 3038.820404] cpts: event pool is empty
[ 3038.824249] cpts: unable to obtain a time stamp
[ 3046.851654] cpts: event pool is empty
[ 3046.855499] cpts: unable to obtain a time stamp
[ 3054.882904] cpts: event pool is empty
[ 3054.886749] cpts: unable to obtain a time stamp
[ 3062.914154] cpts: event pool is empty
[ 3062.917999] cpts: unable to obtain a time stamp
[ 3070.945404] cpts: event pool is empty
[ 3070.949249] cpts: unable to obtain a time stamp
[ 3078.976654] cpts: event pool is empty
[ 3078.980499] cpts: unable to obtain a time stamp
[ 3087.007904] cpts: event pool is empty
[ 3087.011779] cpts: unable to obtain a time stamp
[ 3095.039154] cpts: event pool is empty
[ 3095.043029] cpts: unable to obtain a time stamp
[ 3103.070404] cpts: event pool is empty
[ 3103.074249] cpts: unable to obtain a time stamp
[ 3111.101654] cpts: event pool is empty
[ 3111.105499] cpts: unable to obtain a time stamp
[ 3119.132904] cpts: event pool is empty
[ 3119.136749] cpts: unable to obtain a time stamp
[ 3127.164154] cpts: event pool is empty
[ 3127.167999] cpts: unable to obtain a time stamp
[ 3135.195404] cpts: event pool is empty
[ 3135.199249] cpts: unable to obtain a time stamp
[ 3143.226654] cpts: event pool is empty
[ 3143.230499] cpts: unable to obtain a time stamp
[ 3151.257904] cpts: event pool is empty
[ 3151.261749] cpts: unable to obtain a time stamp
[ 3159.289154] cpts: event pool is empty
[ 3159.292999] cpts: unable to obtain a time stamp


Thanks in advance !!

thanks and regards,

Sarah

  • Hello Sarah,

    The log messages come from the functions below - in /drivers/net/ethernet/ti/cpts.c

    static cycle_t cpts_systim_read(const struct cyclecounter *cc)

    {

    u64 val = 0;

    struct cpts_event *event;

    struct list_head *this, *next;

    struct cpts *cpts = container_of(cc, struct cpts, cc);

    cpts_write32(cpts, TS_PUSH, ts_push);

    if (cpts_fifo_read(cpts, CPTS_EV_PUSH))

    pr_err("cpts: unable to obtain a time stamp\n");

    list_for_each_safe(this, next, &cpts->events) {

    event = list_entry(this, struct cpts_event, list);

    if (event_type(event) == CPTS_EV_PUSH) {

    list_del_init(&event->list);

    list_add(&event->list, &cpts->pool);

    val = event->low;

    break;

    }

    }

    return val;

    }

    /*

    * Returns zero if matching event type was found.

    */

    static int cpts_fifo_read(struct cpts *cpts, int match)

    {

    int i, type = -1;

    u32 hi, lo;

    struct cpts_event *event;

    for (i = 0; i < CPTS_FIFO_DEPTH; i++) {

    if (cpts_fifo_pop(cpts, &hi, &lo))

    break;

    if (list_empty(&cpts->pool)) {

    pr_err("cpts: event pool is empty\n");

    return -1;

    }

    event = list_first_entry(&cpts->pool, struct cpts_event, list);

    event->tmo = jiffies + 2;

    event->high = hi;

    event->low = lo;

    type = event_type(event);

    switch (type) {

    case CPTS_EV_PUSH:

    case CPTS_EV_RX:

    case CPTS_EV_TX:

    list_del_init(&event->list);

    list_add_tail(&event->list, &cpts->events);

    break;

    case CPTS_EV_ROLL:

    case CPTS_EV_HALF:

    case CPTS_EV_HW:

    break;

    default:

    pr_err("cpts: unknown event type\n");

    break;

    }

    if (type == match)

    break;

    }

    return type == match ? 0 : -1;

    }

    I suggest you applying the cpts patches:

    http://patchwork.ozlabs.org/patch/191908/

    In addition, follow the sequence:

    1. Choose appropriate clock as cpts ref clock in UBoot.
    2. Modified the CPSW driver to enable CPTS module and to generate the H/W timestamp for 802.1AS packets. 
    3. Implemented the PTP class driver for Enabling the CPTS as Hardware clock source. 
    4. Implemented the Timekeeping module to hold the upper 32 bit of the 64 bit time in Software 
    5. Implemented the software queue to hold the timestamps and deliver it to the DMA Handlers.
    6. Implemented ioctl call to support start and stop hw time stamping.
    7. Implemented set_multicast_list receiving LLDP multicast packets.
    8. Implemented the adjust clock frequency to change the CPTS ref clock
      • Input ref clock = CLCKINP (20Mhz)
      • Target rate = CLKOUT
      • DCO clock freq = DCOCLK
      • multiplier = M, pre-divider = N, post-divider= M2, fract_mult = Fm
      • CLKOUT = CLKINP*(M+Fm)/(N+1)*M2
      • DCOCLK = CLKOUT*M2
      • REFCLK = CLKINP/(N+1)
    9. Modified the PTPd2 source from source forge to support 802.1AS protocol by the reference from the source from code.google.com as it supports 802.1AS but doesn't support POSIX hardware clock. 
    10. DM814X EVM setup : needs cross compilation for arm architecture 
    11. Test with ptpdv2 in master mode on one DRA7xx EVM and slave mode on another DRA7xx EVM

    Take a look on the links:

    e2e.ti.com/.../1394904

    lists.infradead.org/.../128775.html

    Best regards,

    Yanko

  • Dear Yonko,

    Thanks for your kind replay

    Can you tell me How to choose the reference clock in uboot. Since I am new I could find the clock is

    #define CPTS_REF_CLOCK_NAME "cpsw_cpts_rft_clk"

    static void cpts_clk_init(struct cpts *cpts)
    {
            cpts->refclk = clk_get(NULL, CPTS_REF_CLOCK_NAME);
            if (IS_ERR(cpts->refclk)) {
                    pr_err("Failed to clk_get %s\n", CPTS_REF_CLOCK_NAME);
                    cpts->refclk = NULL;
                    return;
            }
            clk_prepare_enable(cpts->refclk);
    }

    and I could see the error in the dmesg!!

    Regards,

    Sarah

  • Hello Sarah,

    GMAC module in DRA7xx uses following clock signals:
    RMII_50MHz_CLK
    GMAC_MAIN_CLK
    RGMII_5MHZ_CLK
    GMAC_RFT_CLK
    GMII_250MHZ_CLK

    You can configure CPSW with definitions in this file:
    ti-glsdk_dra7xx-evm_7_00_00_04/board-support/u-boot/board/ti/dra7xx/ evm.c

    Please see the thread - e2e.ti.com/.../1190982

    Best regards,
    Yanko
  • Dear Yanko,

     Sorry for being late! Thanks for your kind replay,

    Can You suggest me some step wise procedure or do we have some patches available,

    since I am new to any type of uboot changes kindly help me

    Thanks and Regards,

    Sarah

  • Dear yanko,

    Thanks for the replay !

    Regards,
    Sarah