CPSW -CPTS Hardware timestamping

Hello Mythi,

Please take a look on similar threads:
e2e.ti.com/.../435056

e2e.ti.com/.../1508220

lists.infradead.org/.../251301.html

Best regards,
Yanko

Hi Yanko,

I have tried removing the Hardcoded clock and added the following clocks instead

dpll_gmac_ck
dpll_core_m5_ck

As it is found in the arch/arm/mach_omap2/omap_hwmod_7xx_data.c
cpsw/gmac main_clk="dpll_gmac_ck".
I changed
#define CPTS_REF_CLOCK_NAME "dpll_gmac_ck"


There is no failure of the clock but the sync is not happning!
I only need to know which is the clock doing timestamping..

I refered e2e.ti.com/.../391870
link here it is mentioned that the failure is just a warning . If it is just a warning the cpts->refclk will be null.
and then from where it is taking the timestamp??

Reg,
Mythili

Hello Mythili,

Let's take a look on the picture below:

There are four hardware time stamp inputs (HW1/4_TS_PUSH) that can cause hardware time stamp push events to be loaded into the Event FIFO.

The event is loaded into the event FIFO on the rising edge of the timer, and the PORT_NUMBER field in the CPTS_EVENT_HIGH register indicates the hardware time stamp input that caused the event.

My suggestion is checking clock status of TIMER5 to 8, by registers:

TIMER5_GFCLK Clock Status CM_IPU_CLKSTCTRL[9] CLKACTIVITY_TIMER5_GFCLK
TIMER6_GFCLK Clock Status CM_IPU_CLKSTCTRL[10] CLKACTIVITY_TIMER6_GFCLK
TIMER7_GFCLK Clock Status CM_IPU_CLKSTCTRL[11] CLKACTIVITY_TIMER7_GFCLK

TIMER8_GFCLK Clock Status CM_IPU_CLKSTCTRL[12] CLKACTIVITY_TIMER8_GFCLK

Please set the register:

Clock Domain State Transition Control CM_IPU_CLKSTCTRL[1:0] CLKTRCTRL in 

0x2: SW_WKUP: Start a software forced wake-up transition on the domain.

The time stamp value is a 32-bit value that increments on each CPTS_RFT_CLK rising edge when CPTS_EN is set to 1. When CPTS_EN is cleared to 0, the time stamp value is reset to 0.

In addition:

Time stamp values for every packet transmitted or received on either port of the GMAC_SW are recorded. At the same time, each packet is decoded to determine if it is a valid time sync event. If so, an event is loaded into the Event FIFO for processing containing the recorded time stamp value when the packet was transmitted or received.

Best regards,

Yanko

Hi Yanko,

Thanks ! I ckecked the value of CM_IPU_CLKSTCTRL : 0x4A005540

Out of wihich CM_IPU_CLKSTCTRL[9] is 0
CM_IPU_CLKSTCTRL[10] is 1
CM_IPU_CLKSTCTRL[11] is 0
CM_IPU_CLKSTCTRL[12] is 1

that means that the Timer 6 and Timer 8 are active

__raw_writel(0x2, CM_IPU_CLKSTCTRL);

this is the register write.
Also found the packet checks . time stamp packing as cmsg header in socket.c function

CPTS_EN is set
now I have my timer 6 and 8 enabled and how will I know which is used for timestamp.
The reference clock for the timer is cpts_rft_clk and this is failing. on what the timer gets the rising edge of the clock.
Is there a way to find which clock is sorcing the timers!!


Regards,
Mythili

Mythili,

Let's summarize the necessary steps which you apply in your kernel to enable cpsw clock:

Did you define cpsw clocks in:
board-support/linux/arch/arm/boot/dts/ dra7xx-clocks.dtsi

dpll_gmac_byp_mux: dpll_gmac_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};

dpll_gmac_ck: dpll_gmac_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};

dpll_gmac_m2_ck: dpll_gmac_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};

mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x48484000 0x1000
0x48485200 0xE00>;
#address-cells = <1>;
#size-cells = <1>;
/*
* rx_thresh_pend
* rx_pend
* tx_pend
* misc_pend
*/
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
status = "disabled";

davinci_mdio: mdio@48485000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x48485000 0x100>;
};

cpsw_emac0: slave@48480200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};

cpsw_emac1: slave@48480300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};

phy_sel: cpsw-phy-sel@4a002554 {
compatible = "ti,dra7xx-cpsw-phy-sel";
reg= <0x4a002554 0x4>;
reg-names = "gmii-sel";
};
};

I assume that your issue with cpts_rft_clk is caused by L3_ICLK. It seems that L3_ICLK is not active, because it is the source for CPTS_RFT_CLK.

I suggest you applying the listed set of registers:
Address Values
CM_CLKMODE_DPLL_CORE 0x4a005120 0x00000007
CM_CLKSEL_DPLL_CORE 0x4a00512c 0x0002b30c
CM_DIV_M2_DPLL_CORE 0x4a005130 0x00000001

CM_CLKMODE_DPLL_GMAC 0x4a0052a8 0x00000007
CM_DIV_M2_DPLL_GMAC 0x4a0052b8 0x00000001
CM_DIV_H11_DPLL_GMAC 0x4a0052c0 0x00000001
CM_DIV_H12_DPLL_GMAC 0x4a0052c4 0x00000001

CM_L3INIT_CLKSTCTRL 0x4A009300 [1:0] SW_WKUP - 0x2
CM_GMAC_CLKSTCTRL 0x4A0093C0 [1:0] SW_WKUP - 0x2
Please provide me the values in the register CM_GMAC_CLKSTCTRL

CM_GMAC_GMAC_CLKCTRL 0x4a0093d0 0x08070000
CM_GMAC_GMAC_CLKCTRL[1:0] MODULEMODE - 0x1 Module is managed automatically by HW according to clock domain transition.

PM_IPU_PWRSTCTRL 0x4AE06500 1:0 POWERSTATE - 0x3: ON State

Check the PRCM configuration for GMAC module.

Best regards,
Yanko

Hi,

Thanks for the replay

I don't have dra7xx-clocks.dtsi file and I do the following in the dra7.dtsi file

  dpll_gmac_byp_mux: dpll_gmac_byp_mux {
                                #clock-cells = <0>;
                                compatible = "ti,mux-clock";
                                clocks = <&sys_clkin1>;
                                ti,bit-shift = <23>;
                                reg = <0x02b4>;
               };

               dpll_gmac_ck: dpll_gmac_ck {
                               #clock-cells = <0>;
                               compatible = "ti,omap4-dpll-clock";
                               clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
                               reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
               };

               dpll_gmac_m2_ck: dpll_gmac_m2_ck {
                               #clock-cells = <0>;
                               compatible = "ti,divider-clock";
                               clocks = <&dpll_gmac_ck>;
                               ti,max-div = <31>;
                               ti,autoidle-shift = <8>;
                               reg = <0x02b8>;
                               ti,index-starts-at-one;
                               ti,invert-autoidle-bit;
               };


                gmac: ethernet@48484000 {
                        compatible = "ti,cpsw";
                        ti,hwmods = "gmac";
                        clocks = <&dpll_gmac_ck>;
                        clock-names = "fck", "cpts";
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
                        no_bd_ram = <0>;
                        rx_descs = <64>;
                        mac_control = <0x20>;
                        slaves = <2>;
                        active_slave = <0>;
                        cpts_clock_mult = <0x80000000>;
                        cpts_clock_shift = <29>;
                        reg = <0x48484000 0x800
                               0x48485200 0x100>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        /*
                         * rx_thresh_pend
                         * rx_pend
                         * tx_pend
                         * misc_pend
                         */
                        interrupts = <23 334 0x4>,
                                     <23 335 0x4>,
                                     <23 336 0x4>,
                                     <23 337 0x4>;
                        ranges;
                        status = "disabled";

                        davinci_mdio: mdio@48485000 {
                                compatible = "ti,davinci_mdio";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x48485000 0x100>;
                        };

                        cpsw_emac0: slave@48484200 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };

                        cpsw_emac1: slave@48484300 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };
                        phy_sel: cpsw-phy-sel@4a002554 {
                                compatible = "ti,dra7xx-cpsw-phy-sel";
                                reg= <0x4a002554 0x4>;
                                reg-names = "gmii-sel";
                        };
                };

Please tell me if it is correct ..

Regards,

mythili

Hello Mythili,

I agree with your modifications in dra7.dtsi file. However, the better approach is using the newer release of GLSDK.
In the new release the CPSW has the necessary definitions in:
dra7xx-clocks.dtsi
dra7.dtsi
dra7-evm.dts

For more detail information take a look in: GLSDK 7.01.00.03 - downloads.ti.com/.../index_FDS.html

If you have plans to use GLSDK 6.04 your must add following definitions in your dra7.dtsi:
ti-glsdk_dra7xx-evm_7_01_00_03/board-support/linux/arch/arm/boot/dts/ dra7xx-clocks.dtsi

dpll_gmac_x2_ck: dpll_gmac_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_gmac_ck>;
};

dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};

dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};

dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x02c8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};

dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};

gmii_m_clk_div: gmii_m_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_gmac_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
};


gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
ti,dividers = <2>;
};

gmac_rft_clk_mux: gmac_rft_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
ti,bit-shift = <25>;
reg = <0x13d0>;
};

gmac_250m_dclk_div: gmac_250m_dclk_div {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
ti,max-div = <64>;
reg = <0x019c>;
ti,index-power-of-two;
};

Best regards,
Yanko

Hi yanko,


I do the following in dra7.dtsi file


dpll_gmac_byp_mux: dpll_gmac_byp_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>;
ti,bit-shift = <23>;
reg = <0x02b4>;
};

dpll_gmac_ck: dpll_gmac_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};

dpll_gmac_m2_ck: dpll_gmac_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x02b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};


gmac: ethernet@48484000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x48484000 0x800
0x48485200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
/*
* rx_thresh_pend
* rx_pend
* tx_pend
* misc_pend
*/
interrupts = <0 50 0x4>,
<0 51 0x4>,
<0 52 0x4>,
<0 52 0x4>;
ranges;
status = "disabled";

davinci_mdio: mdio@48485000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x48485000 0x100>;
};

cpsw_emac0: slave@48484200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};

cpsw_emac1: slave@48484300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
};


2. CM_L3INIT_CLKSTCTRL value is :0x4A009300
CM_GMAC_CLKSTCTRL value is :0x4A0093C0
and I don't find any PM_IPU_PWRSTCTRL.



3. You have said
"
I suggest you applying the listed set of registers:
Address Values
CM_CLKMODE_DPLL_CORE 0x4a005120 0x00000007
CM_CLKSEL_DPLL_CORE 0x4a00512c 0x0002b30c
CM_DIV_M2_DPLL_CORE 0x4a005130 0x00000001

CM_CLKMODE_DPLL_GMAC 0x4a0052a8 0x00000007
CM_DIV_M2_DPLL_GMAC 0x4a0052b8 0x00000001
CM_DIV_H11_DPLL_GMAC 0x4a0052c0 0x00000001
CM_DIV_H12_DPLL_GMAC 0x4a0052c4 0x00000001
"

I have the register address value same as mentioned. what you meen here is to change the address value of the reg or to change the values in the reg pointed by the address. cannot understand a bit.
Please tell me if my device tree(.dtsi) changed are correct

regards,
mythili

Thanks for the replay
I am trying to download GLSDK 7.01.00.03


Regards,
mythili

Hi Yanko,

I have tried installing the GLADK 7.01.00.03 and the board is booted up.

1. Linux PTP code running: Hardware timestamping done but as of previous no synchronization
2. As you have mentioned I have checked the Following Registers
CM_IPU_CLKSTCTRL : 0x4A005540
CM_IPU_CLKSTCTRL[9] is 0
CM_IPU_CLKSTCTRL[10] is 1
CM_IPU_CLKSTCTRL[11] is 0
CM_IPU_CLKSTCTRL[12] is 1

CM_L3INIT_CLKSTCTRL 0x4A009300
CM_GMAC_CLKSTCTRL 0x4A0093C0

The following registrer address are the same
CM_CLKMODE_DPLL_CORE 0x4a005120
CM_CLKSEL_DPLL_CORE 0x4a00512c
CM_DIV_M2_DPLL_CORE 0x4a005130

CM_CLKMODE_DPLL_GMAC 0x4a0052a8
CM_DIV_M2_DPLL_GMAC 0x4a0052b8
CM_DIV_H11_DPLL_GMAC 0x4a0052c0
CM_DIV_H12_DPLL_GMAC 0x4a0052c4

I dont get what is the vaue you have provided to these above address.

Still PTP code output is

ptp4l[43.811]: selected /dev/ptp0 as PTP clock
ptp4l[43.812]: port 1: get_ts_info not supported
ptp4l[43.898]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[43.898]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[43.899]: port 1: received SYNC without timestamp
ptp4l[44.772]: port 1: new foreign master 001560.fffe.52d0c9-1
ptp4l[48.772]: selected best master clock 001560.fffe.52d0c9
ptp4l[48.772]: foreign master not using PTP timescale
ptp4l[48.772]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[49.887]: master offset 1435432007168949916 s0 freq +0 path delay 32594
ptp4l[50.887]: master offset 1435432007232987909 s1 freq +1000000 path delay 32572
ptp4l[51.887]: master offset 62973363 s2 freq +1000000 path delay 32551
ptp4l[51.887]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[52.887]: master offset 125947565 s2 freq +1000000 path delay 32443
ptp4l[53.887]: master offset 188922348 s2 freq +1000000 path delay 32551
ptp4l[54.887]: master offset 251895796 s2 freq +1000000 path delay 32572
ptp4l[55.887]: master offset 314870188 s2 freq +1000000 path delay 32464
ptp4l[56.887]: master offset 377844032 s2 freq +1000000 path delay 32464
ptp4l[57.887]: master offset 440819415 s2 freq +1000000 path delay 32275
ptp4l[58.887]: master offset 503792929 s2 freq +1000000 path delay 32275
ptp4l[59.888]: master offset 566766550 s2 freq +1000000 path delay 32275
ptp4l[60.888]: master offset 629740506 s2 freq +1000000 path delay 32299
ptp4l[61.888]: master offset 692713771 s2 freq +1000000 path delay 32464
ptp4l[62.888]: master offset 755688197 s2 freq +1000000 path delay 32456
ptp4l[63.888]: master offset 818661951 s2 freq +1000000 path delay 32456
ptp4l[64.888]: master offset 881635992 s2 freq +1000000 path delay 32530
ptp4l[65.888]: master offset 944609966 s2 freq +1000000 path delay 32647
ptp4l[66.888]: master offset 1007584218 s2 freq +1000000 path delay 32437
ptp4l[67.888]: master offset 1070558828 s2 freq +1000000 path delay 32647

Please tell me how to proceed!!


Regards,
mythili

Hello Mythili,

Could you explain me how you installed ptp4 software in your GLSDK?

Could you run some commands:

ptp4l –i eth0 –f /etc/ptp4l.conf –s
phc2sys –s eth0 –c CLOCK_REALTIME –w
pmc –u –b 0 ‘GET CURRENT_DATA_SET’

Share the log when you run these commands.

Best regards,
Yanko

Hi Yanko,

I have downloaded the ptp source from the net. linuxptp-asi1230-master.

and i cross compile the same using arm-linux-gnueabi- tool chain and do the following
 ./ptp4l -P -2 -H -p /dev/ptp0 -i eth0 -m -s
ptp4l[847.913]: selected /dev/ptp0 as PTP clock
ptp4l[847.914]: port 1: get_ts_info not supported
ptp4l[847.978]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[847.978]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[850.953]: port 1: new foreign master f8bc12.fffe.8c14a8-1
ptp4l[854.794]: selected best master clock 7c669d.fffe.f1b614
ptp4l[854.955]: selected best master clock f8bc12.fffe.8c14a8
ptp4l[854.955]: foreign master not using PTP timescale
ptp4l[854.955]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[855.955]: master offset -1676293251987403 s0 freq      +0 path delay     45642
ptp4l[856.956]: master offset -1676293187965918 s1 freq +1000000 path delay     45860
ptp4l[857.956]: master offset   62952983 s2 freq +1000000 path delay     46078
ptp4l[857.957]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[858.957]: master offset  125907244 s2 freq +1000000 path delay     45948
ptp4l[859.958]: master offset  188861703 s2 freq +1000000 path delay     45730
ptp4l[860.958]: master offset  251818531 s2 freq +1000000 path delay     43036
ptp4l[861.959]: master offset  314777381 s2 freq +1000000 path delay     39957
ptp4l[862.959]: master offset  377730469 s2 freq +1000000 path delay     39957
ptp4l[863.960]: master offset  440683161 s2 freq +1000000 path delay     40151
ptp4l[864.961]: master offset  503635441 s2 freq +1000000 path delay     39677
ptp4l[865.961]: master offset  566588952 s2 freq +1000000 path delay     39677
ptp4l[866.962]: master offset  629542766 s2 freq +1000000 path delay     39677
ptp4l[867.962]: master offset  692497188 s2 freq +1000000 path delay     39243
ptp4l[868.963]: master offset  755450664 s2 freq +1000000 path delay     39094
ptp4l[869.963]: master offset  818406196 s2 freq +1000000 path delay     39094

As you have mentioned  I don't have conf file in etc

./pmc -u -b 0 'GET CURRENT_DATA_SET'   
sending: GET CURRENT_DATA_SET

root@dra7xx-evm:/opt/opt# ./phc2sys -s eth0 -c CLOCK_REALTIME
unknown clock eth0: No such file or directory
valid source clock must be selected.

usage: phc2sys [options]

 -c [dev|name]  slave clock (CLOCK_REALTIME)
 -d [dev]       master PPS device
 -s [dev|name]  master clock
 -E [pi|linreg] clock servo (pi)
 -P [kp]        proportional constant (0.7)
 -I [ki]        integration constant (0.3)
 -S [step]      step threshold (disabled)
 -F [step]      step threshold only on start (0.00002)
 -R [rate]      slave clock update rate in HZ (1.0)
 -N [num]       number of master clock readings per update (5)
 -O [offset]    slave-master time offset (0)
 -L [limit]     sanity frequency limit in ppb (200000000)
 -u [num]       number of clock updates in summary stats (0)
 -w             wait for ptp4l
 -n [num]       domain number (0)
 -x             apply leap seconds by servo instead of kernel
 -l [num]       set the logging level to 'num' (6)
 -m             print messages to stdout
 -q             do not print messages to the syslog
 -v             prints the software version and exits
 -h             prints this message and exits
 and When I run

./phc2sys -s /dev/ptp0 -c CLOCK_REALTIME -w -m                                                              
phc2sys[1085.555]: Waiting for ptp4l...
phc2sys[1086.556]: Waiting for ptp4l...
phc2sys[1087.558]: Waiting for ptp4l...

./phc2sys -s /dev/ptp0 -c CLOCK_REALTIME -O 0 -m                                                          
phc2sys[1111.744]: phc offset -1676336887158996 s0 freq -500000 delay   3580
phc2sys[1112.744]: phc offset -1676336949601230 s1 freq -62936018 delay   3743
phc2sys[1113.745]: failed to adjust the clock: Invalid argument
phc2sys[1113.745]: phc offset -62426040 s2 freq -81663830 delay   3580
phc2sys[1114.745]: failed to adjust the clock: Invalid argument
phc2sys[1114.745]: phc offset -124860938 s2 freq -100000000 delay   3743
phc2sys[1115.745]: phc offset -187285743 s2 freq -100000000 delay   2929
phc2sys[1116.746]: phc offset -249702333 s2 freq -100000000 delay   2767

Regards,

mythili

Hi Yanko,

The issue is solved , This is due to the fact that the HW clock is faster than the PC clock and I did the following to the cpts driver

....

static int cpts_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
        u64 adj;
        u32 diff, mult;
        int neg_adj = 0;
        unsigned long flags;
        struct cpts *cpts = container_of(ptp, struct cpts, info);

        if (ppb < 0) {
                neg_adj = 1;
                ppb = -ppb;
        }
    
        //mult = cpts->cc_mult;
        mult = cpts->cc.mult;
        adj = mult;
        adj *= ppb;
        diff = div_u64(adj, 1000000000ULL);

        spin_lock_irqsave(&cpts->lock, flags);

        timecounter_read(&cpts->tc);

        cpts->cc.mult = neg_adj ? mult - diff : mult + diff;
             spin_unlock_irqrestore(&cpts->lock, flags);

        return 0;
}

Regards,

mythili

Hi Yanko,

I do have the following error I follow the GLSDK 7.01.00.03 and do the amixer setting

I get the following

root@dra7xx-evm:/opt/opt# amixer sset 'Left DAC Mux',0 'DAC_L2'

[ 2900.528915] tlv320aic3x-codec 0-0019: ASoC: Left DAC Mux DAPM update failed: -121

Simple mixer control 'Left DAC Mux',0

 Capabilities: enum

 Items: 'DAC_L1' 'DAC_L3' 'DAC_L2'

 Item0: 'DAC_L2'

root@dra7xx-evm:/opt/opt# amixer sset 'Right DAC Mux',0 'DAC_R2'

[ 2913.688860] tlv320aic3x-codec 0-0019: ASoC: Right DAC Mux DAPM update failed: -121

Simple mixer control 'Right DAC Mux',0

 Capabilities: enum

 Items: 'DAC_R1' 'DAC_R3' 'DAC_R2'

 Item0: 'DAC_R2'

The next time when i do it I don't get any error

root@dra7xx-evm:/opt/opt# amixer sset 'Right DAC Mux',0 'DAC_R2'

Simple mixer control 'Right DAC Mux',0

 Capabilities: enum

 Items: 'DAC_R1' 'DAC_R3' 'DAC_R2'

 Item0: 'DAC_R2'

root@dra7xx-evm:/opt/opt# amixer sset 'Left DAC Mux',0 'DAC_L2'

Simple mixer control 'Left DAC Mux',0

 Capabilities: enum

 Items: 'DAC_L1' 'DAC_L3' 'DAC_L2'

 Item0: 'DAC_L2'

When I do aplay I get the following error.

root@dra7xx-evm:/opt/opt# aplay Mun_Andhi-VmusiQ.Com.wav
Playing WAVE 'Mun_Andhi-VmusiQ.Com.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
aplay: aplay.c:1284: set_params: Assertion `err >= 0' failed.
Aborted by signal Aborted...

Please guide me on this regards

regards,

Mythili

Hello Mythili,

The AIC3016 codec is connected to MCASP3 module. I suggest you to check if McASP3 module is enabled.

Try to enable McASP by registers:

CM_L4PER2_MCASP3_CLKCTRL[1:0] MODULEMODE - 0x2: Module is explicitly enabled.

I saw that you use the commands listed in GLSDK guides:

Running aplay and arecord application

To playback/record on the evm via headset/mic, please make sure the following amixer settings are done:

• For playback via headset, enter the following at prompt target#

  amixer sset 'Left DAC Mux',0 'DAC_L2'
  amixer sset 'Right DAC Mux',0 'DAC_R2'
  amixer cset name='HP Playback Switch' On
  amixer cset name='Line Playback Switch' Off
  amixer cset name='PCM Playback Volume' 127

Once these settings are successful, use aplay application for playback:

  target #  aplay <path_to_example_audio>.wav

• For recording via Mic In

  amixer cset name='Left PGA Mixer Mic3L Switch' On
  amixer cset name='Right PGA Mixer Mic3L Switch' On
  amixer cset name='Left PGA Mixer Line1L Switch' off
  amixer cset name='Right PGA Mixer Line1R Switch' off
  amixer cset name='PGA Capture Switch' on
  amixer cset name='PGA Capture Volume' 6

Best regards,

Yanko

Hi Mythili,

Please take a look and use McASP3 configuration from the patches:
review.omapzoom.org
review.omapzoom.org

It seems that McASP3 is disabled in device tree.

Best regards,
Yanko

Hi Yanko,

Thanks for your replay!

Is this patch for the GLSDK 6.04 kernel. Alsa was working perfectly in that 6.04 (linux 3.8).

But I could not find the similar thing in 7.01(linux 3.14) kernel /Cannot apply the patch.

Is there some other change needed. or the changes that has been done to 7.01 kernel from that of 6.04 is causing this issue.

Regards,

Sarah.

Hello Sarah,

I don't have clear view on the new modules in GLSDK and I cannot point you all of necessary changes.

I suggest you to check all patches related with McASP3, available in review.omapzoom.org
Related Changes (9)
ASoC: dra7-evm: Use McASP3 with eDMA
ARM: dra7xx: Add eDMA hwmod data and dts node
ASoC: davinci-mcasp: Warn when overflows/underflows occur
ASoC: davinci-mcasp: Add support for DRA7 with eDMA
ASoC: davinci-mcasp: Fix dma_addr when using DAT port
ASoC: davinci-pcm: Add support on DRA7 platforms
ASoC: davinci-pcm: Use more sane PCM hardware params
ASoC: davinci-pcm: Fix DMA data params pointer
dmaengine: omap-dma: Enable packed accesses for cyclic transfers

ARM: dts: DRA7xx: Add DATA Port to McASP3 node - review.omapzoom.org
Use DATA Port Workaround for DRA7xx - review.omapzoom.org
omap-dma: DATA Port Workaround for DRA7xx - review.omapzoom.org

Afterwards you can test all changes in your system.

Best regards,
Yanko

Hi Yanko,

I have gone through all pactches and applied most fo them. Then I found that sw8 in the hardware has the connection with audio. hence place as sw8(1) on and sw8(2) and I got audio for aplay input.bin -r 8000 -c 2
If I make it to 44100Hz I get
aplay: aplay.c:1284: set_params: Assertion `err >= 0' failed.
Aborted by signal Aborted...

I works fine for 48000Hz

I can't figure out this behaviour,Please guide me on this regards.

Regards,
Mythili.

Hello Mythili,

To enable 44100Hz frequency you must select SYS_CLK2 as AIC3106_MCLK. The default configuration uses SYS_CLK1 as AIC3106_MCLK.
For this purpose apply the following modification in the registers:
CM_L4PER2_MCASP3_CLKCTRL[27:24] CLKSEL_AHCLKX - 0x7: Selects SYS_CLK2

You cannot achieve 44.1KHz MCLK if you use SYS_CLK1

If the modification above don't affect the system behavior apply and the change in the register:
CM_CLKSEL_ABE_PLL_SYS[0] CLKSEL - 0x1: Selects SYS_CLK2

Best regards,
Yanko

You said you made a change to the cpts driver, but all I can see is that you commented out the line and repeated the same line of code.

//mult = cpts->cc_mult;
 mult = cpts->cc.mult;

Is this what you intended?