SPL and U-Boot porting using following SDK ti-processor-sdk-linux-am335x-evm-01.00.00.03-Linux-x86-Install

Hello All,

Please let me know if you need any other inputs.

Best Regards,

GSR

Hello,

Refer to the below pointers:

http://processors.wiki.ti.com/index.php/Linux_Core_U-Boot_User%27s_Guide
http://processors.wiki.ti.com/index.php/AM335x_U-Boot_User%27s_Guide
processors.wiki.ti.com/.../Sitara_Linux_Training:_UBoot_Board_Port
processors.wiki.ti.com/.../Sitara_Linux_Training:_uboot_linux_debug_with_ccsv5_sdk7
processors.wiki.ti.com/.../Understanding_u-boot-min_startup_for_DM814x

BR
Pavel

Hi Pavel,

Thank You for the URLs.

At the end of the following URL: http://processors.wiki.ti.com/index.php/Understanding_u-boot-min_startup_for_DM814x

there is a function call sequence. I see that s_init exits. But after that no prints on the console.

Do you have any inputs on what could be wrong?

Best Regards,

GSR

GSR,

1258021 said:

I see that s_init exits. But after that no prints on the console.

So, you are sure that your flow enters in s_init(), exit from s_init() and then hang? s_init() is the one from the below file? When you load this in TI EVM, what is the next step there (next step right after s_init)?

ti-processor-sdk-linux-am335x-evm-01.00.00.00/board-support/u-boot-2014.07-g7e537bf/arch/arm/cpu/armv7/am33xx/board.c

void s_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
    rtc_only();
#endif
    /*
     * The ROM will only have set up sufficient pinmux to allow for the
     * first 4KiB NOR to be read, we must finish doing what we know of
     * the NOR mux in this space in order to continue.
     */
#ifdef CONFIG_NOR_BOOT
    enable_norboot_pin_mux();
#endif
    /*
     * Save the boot parameters passed from romcode.
     * We cannot delay the saving further than this,
     * to prevent overwrites.
     */
#ifdef CONFIG_SPL_BUILD
    save_omap_boot_params();
#endif
    watchdog_disable();
    timer_init();
    set_uart_mux_conf();
    setup_clocks_for_console();
    uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
    gd->baudrate = CONFIG_BAUDRATE;
    serial_init();
    gd->have_console = 1;
#elif defined(CONFIG_SPL_BUILD)
    gd = &gdata;
    preloader_console_init();
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
    /* Enable RTC32K clock */
    rtc32k_enable();
#endif
#ifdef CONFIG_SPL_BUILD
    board_early_init_f();
    sdram_init();
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
    update_rtc_magic();
#endif
}

Hi Pavel,

I see below getting printed in case of EVM

board_init_f weak (vi ./arch/arm/lib/spl.c)

For our board I do not see board_init_f being printed and hangs.

board_init_f is called from _main which is in the following file (./arch/arm/lib/crt0.S)

In ./arch/arm/lib/crt0.S file if I move the  board_init_f function before re configuring SP to CONFIG_SPL_STACK the function is called.

Otherwise my board hangs.

As CONFIG_SPL_STACK base address is 0x80000000, does it mean that SDRAM is not functional in our case?

Does SPL provide any SDRAM test code before configuring SP in crt0.s to a value which falls in the range of SDRAM.

Best Regards,

GSR

Another approach can be to undefine the CONFIG_SPL_STACK/0x80000000, and thus use the CONFIG_SYS_INIT_SP_ADDR/0x40310000, which is location from the internal OCMC RAM.

ENTRY(_main)

/*
* Set up initial C runtime environment and call board_init_f(0).
*/

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =(CONFIG_SPL_STACK)
#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
#endif

Hi Pavel,

Thank you for your valuable inputs. When I un define the flag CONFIG_SPL_STACK, the code goes further.

I guess with SDRAM issue the SPL may not be able to write U-Boot to SDRAM and we have to fix that first.

We are sure that SDRAM is functional as we verified it in CCS after Software Levelling. Also we wrote small piece of code based on the following URL:http://www.barrgroup.com/Embedded-Systems/How-To/Memory-Test-Suite-C a

Thank You for your valuable time.

Best Regards,

GSR