1033.mux.c
/* * mux.c * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> #include <asm/io.h> #include <i2c.h> #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ {-1}, }; static struct module_pin_mux uart1_pin_mux[] = { {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ {-1}, }; static struct module_pin_mux uart2_pin_mux[] = { {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ {-1}, }; static struct module_pin_mux uart3_pin_mux[] = { {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ {-1}, }; static struct module_pin_mux uart4_pin_mux[] = { {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ {-1}, }; static struct module_pin_mux uart5_pin_mux[] = { {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ {-1}, }; static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; static struct module_pin_mux mmc0_no_cd_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ {-1}, }; static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; static struct module_pin_mux mmc1_pin_mux[] = { {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ {-1}, }; static struct module_pin_mux i2c0_pin_mux[] = { {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux i2c1_pin_mux[] = { {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ {-1}, }; static struct module_pin_mux spi0_pin_mux[] = { {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ {-1}, }; static struct module_pin_mux gpio0_7_pin_mux[] = { {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ {-1}, }; static struct module_pin_mux rgmii1_pin_mux[] = { {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, }; static struct module_pin_mux mii1_pin_mux[] = { {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, }; #ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ #endif {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; #elif defined(CONFIG_NOR) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ {-1}, }; #endif #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { configure_module_pin_mux(bone_norcape_pin_mux); } #endif void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); } void enable_uart1_pin_mux(void) { configure_module_pin_mux(uart1_pin_mux); } void enable_uart2_pin_mux(void) { configure_module_pin_mux(uart2_pin_mux); } void enable_uart3_pin_mux(void) { configure_module_pin_mux(uart3_pin_mux); } void enable_uart4_pin_mux(void) { configure_module_pin_mux(uart4_pin_mux); } void enable_uart5_pin_mux(void) { configure_module_pin_mux(uart5_pin_mux); } void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } /* * The AM335x GP EVM, if daughter card(s) are connected, can have 8 * different profiles. These profiles determine what peripherals are * valid and need pinmux to be configured. */ #define PROFILE_NONE 0x0 #define PROFILE_0 (1 << 0) #define PROFILE_1 (1 << 1) #define PROFILE_2 (1 << 2) #define PROFILE_3 (1 << 3) #define PROFILE_4 (1 << 4) #define PROFILE_5 (1 << 5) #define PROFILE_6 (1 << 6) #define PROFILE_7 (1 << 7) #define PROFILE_MASK 0x7 #define PROFILE_ALL 0xFF /* CPLD registers */ #define I2C_CPLD_ADDR 0x35 #define CFG_REG 0x10 static unsigned short detect_daughter_board_profile(void) { unsigned short val; if (i2c_probe(I2C_CPLD_ADDR)) return PROFILE_NONE; if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) return PROFILE_NONE; return (1 << (val & PROFILE_MASK)); } void enable_board_pin_mux(struct am335x_baseboard_id *header) { //if (board_is_evm_sk(header)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); //configure_module_pin_mux(mmc0_pin_mux_sk_evm); //} #if 0 /* Do board-specific muxes. */ if (board_is_bone(header)) { /* Beaglebone pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ #ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) configure_module_pin_mux(nand_pin_mux); #endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } } else if (board_is_idk(header)) { /* * Industrial Motor Control (IDK) * note: IDK console is on UART3 by default. * So u-boot mus be build with CONFIG_SERIAL4 and * CONFIG_CONS_INDEX=4 */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); } else if (board_is_evm_sk(header)) { /* Starter Kit EVM */ //configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); //configure_module_pin_mux(mmc0_pin_mux_sk_evm); } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc1_pin_mux); /* #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(nand_pin_mux); #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); #endif */ } else { puts("Unknown board, cannot configure pinmux."); hang(); } #endif }
4113.board.c
/* * board.c * * Board functions for TI AM335X based boards * * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include <asm/io.h> #include <asm/emif.h> #include <asm/gpio.h> #include <i2c.h> #include <miiphy.h> #include <cpsw.h> #include <power/tps65217.h> #include <power/tps65910.h> #include <environment.h> #include <watchdog.h> #include <environment.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* * Read header information from EEPROM into global structure. */ static int read_eeprom(struct am335x_baseboard_id *header) { #if 0 /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { puts("Could not probe the EEPROM; something fundamentally " "wrong on the I2C bus.\n"); return -ENODEV; } /* read the eeprom using i2c */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); return -EIO; } if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something " "fundamentally wrong on the I2C bus.\n"); return -EIO; } if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", header->magic); return -EINVAL; } } #endif } #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, .cmd1csratio = MT47H128M16RT25E_RATIO, .cmd2csratio = MT47H128M16RT25E_RATIO, }; static const struct emif_regs ddr2_emif_reg_data = { .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, }; static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J128MJT125_RD_DQS, .datawdsratio0 = MT41J128MJT125_WR_DQS, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, }; static const struct ddr_data ddr3_beagleblack_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, }; static const struct ddr_data ddr3_jvs_data = { .datardsratio0 = MT41J128M16JT125_RD_DQS, .datawdsratio0 = MT41J128M16JT125_WR_DQS, .datafwsratio0 = MT41J128M16JT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128M16JT125_PHY_WR_DATA, }; static const struct ddr_data ddr3_evm_data = { .datardsratio0 = MT41J512M8RH125_RD_DQS, .datawdsratio0 = MT41J512M8RH125_WR_DQS, .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, /* .datardsratio0 = MT41J128M16JT125_RD_DQS, .datawdsratio0 = MT41J128M16JT125_WR_DQS, .datafwsratio0 = MT41J128M16JT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128M16JT125_PHY_WR_DATA, */ }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd1csratio = MT41J128MJT125_RATIO, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd2csratio = MT41J128MJT125_RATIO, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; static const struct cmd_control ddr3_jvs_cmd_ctrl_data = { .cmd0csratio = MT41J128M16JT125_RATIO, .cmd0iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd0dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, .cmd1csratio = MT41J128M16JT125_RATIO, .cmd1iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd1dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, .cmd2csratio = MT41J128M16JT125_RATIO, .cmd2iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd2dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd1csratio = MT41J512M8RH125_RATIO, .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd2csratio = MT41J512M8RH125_RATIO, .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, /* .cmd0csratio = MT41J128M16JT125_RATIO, .cmd0iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd0dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, .cmd1csratio = MT41J128M16JT125_RATIO, .cmd1iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd1dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, .cmd2csratio = MT41J128M16JT125_RATIO, .cmd2iclkout = MT41J128M16JT125_INVERT_CLKOUT, // .cmd2dldiff = MT41J128M16JT125_DLL_LOCK_DIFF, */ }; static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41J128MJT125_EMIF_SDCFG, .ref_ctrl = MT41J128MJT125_EMIF_SDREF, .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, .zq_config = MT41J128MJT125_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; static struct emif_regs ddr3_jvs_emif_reg_data = { .sdram_config = MT41J128M16JT125_EMIF_SDCFG, .ref_ctrl = MT41J128M16JT125_EMIF_SDREF, .sdram_tim1 = MT41J128M16JT125_EMIF_TIM1, .sdram_tim2 = MT41J128M16JT125_EMIF_TIM2, .sdram_tim3 = MT41J128M16JT125_EMIF_TIM3, .zq_config = MT41J128M16JT125_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41J128M16JT125_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; static struct emif_regs ddr3_beagleblack_emif_reg_data = { .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, .zq_config = MT41K256M16HA125E_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, }; static struct emif_regs ddr3_evm_emif_reg_data = { .sdram_config = MT41J512M8RH125_EMIF_SDCFG, .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, .zq_config = MT41J512M8RH125_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, /* .sdram_config = MT41J128M16JT125_EMIF_SDCFG, .ref_ctrl = MT41J128M16JT125_EMIF_SDREF, .sdram_tim1 = MT41J128M16JT125_EMIF_TIM1, .sdram_tim2 = MT41J128M16JT125_EMIF_TIM2, .sdram_tim3 = MT41J128M16JT125_EMIF_TIM3, .zq_config = MT41J128M16JT125_ZQ_CFG, .emif_ddr_phy_ctlr_1 = MT41J128M16JT125_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, */ }; #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { /* break into full u-boot on 'c' */ if (serial_tstc() && serial_getc() == 'c') return 1; #ifdef CONFIG_SPL_ENV_SUPPORT env_init(); env_relocate_spec(); if (getenv_yesno("boot_os") != 1) return 1; #endif return 0; } #endif #define OSC (V_OSCK/1000000) const struct dpll_params dpll_ddr = { 266, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_ddr_jvs = { 400, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_ddr_evm_sk = { 303, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_ddr_bone_black = { 400, OSC-1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { struct am335x_baseboard_id header; int mpu_vdd; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); if (board_is_bone(&header) || board_is_bone_lt(&header)) { /* BeagleBone PMIC Code */ int usb_cur_lim; /* * Only perform PMIC configurations if board rev > A1 * on Beaglebone White */ if (board_is_bone(&header) && !strncmp(header.version, "00A1", 4)) return; if (i2c_probe(TPS65217_CHIP_PM)) return; /* * On Beaglebone White we need to ensure we have AC power * before increasing the frequency. */ if (board_is_bone(&header)) { uchar pmic_status_reg; if (tps65217_reg_read(TPS65217_STATUS, &pmic_status_reg)) return; if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { puts("No AC power, disabling frequency switch\n"); return; } } /* * Override what we have detected since we know if we have * a Beaglebone Black it supports 1GHz. */ if (board_is_bone_lt(&header)) dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ if (dpll_mpu_opp100.m == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; } else { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; } if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("tps65217_reg_write failure\n"); /* Set DCDC3 (CORE) voltage to 1.125V */ if (tps65217_voltage_update(TPS65217_DEFDCDC3, TPS65217_DCDC_VOLT_SEL_1125MV)) { puts("tps65217_voltage_update failure\n"); return; } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { puts("tps65217_voltage_update failure\n"); return; } /* * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ if (board_is_bone(&header)) { if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); } else { if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); } if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); } else { int sil_rev; /* * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all * MPU frequencies we support we use a CORE voltage of * 1.1375V. For MPU voltage we need to switch based on * the frequency we are running at. */ if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) return; /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. */ sil_rev = readl(&cdev->deviceid) >> 28; mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu_opp100.m); /* Tell the TPS65910 to use i2c */ tps65910_set_i2c_control(); /* First update MPU voltage. */ if (tps65910_voltage_update(MPU, mpu_vdd)) return; /* Second, update the CORE voltage. */ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) return; /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); } /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } const struct dpll_params *get_dpll_ddr_params(void) { struct am335x_baseboard_id header; enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* if (board_is_evm_sk(&header)) return &dpll_ddr_evm_sk; else if (board_is_bone_lt(&header)) return &dpll_ddr_bone_black; else if (board_is_evm_15_or_later(&header)) return &dpll_ddr_evm_sk; else */ return &dpll_ddr_jvs; } void set_uart_mux_conf(void) { #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ #ifdef CONFIG_SERIAL2 enable_uart1_pin_mux(); #endif /* CONFIG_SERIAL2 */ #ifdef CONFIG_SERIAL3 enable_uart2_pin_mux(); #endif /* CONFIG_SERIAL3 */ #ifdef CONFIG_SERIAL4 enable_uart3_pin_mux(); #endif /* CONFIG_SERIAL4 */ #ifdef CONFIG_SERIAL5 enable_uart4_pin_mux(); #endif /* CONFIG_SERIAL5 */ #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ } void set_mux_conf_regs(void) { __maybe_unused struct am335x_baseboard_id header; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); enable_board_pin_mux(&header); } const struct ctrl_ioregs ioregs_evmsk = { .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, }; const struct ctrl_ioregs ioregs_bonelt = { .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, }; const struct ctrl_ioregs ioregs_evm15 = { .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, }; const struct ctrl_ioregs ioregs = { .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, }; const struct ctrl_ioregs ioregs_jvs = { .cm0ioctl = MT41J128M16JT125_IOCTRL_VALUE, .cm1ioctl = MT41J128M16JT125_IOCTRL_VALUE, .cm2ioctl = MT41J128M16JT125_IOCTRL_VALUE, .dt0ioctl = MT41J128M16JT125_IOCTRL_VALUE, .dt1ioctl = MT41J128M16JT125_IOCTRL_VALUE, }; void sdram_init(void) { __maybe_unused struct am335x_baseboard_id header; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); #if 0 if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. */ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); } if (board_is_evm_sk(&header)) //config_ddr(303, &ioregs_evmsk, &ddr3_data, // &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); config_ddr(303, MT41J128M16JT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt(&header)) config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later(&header)) config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else #endif gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); config_ddr(400, MT41J128M16JT125_IOCTRL_VALUE, &ddr3_jvs_data, &ddr3_jvs_cmd_ctrl_data, &ddr3_jvs_emif_reg_data,0); } #endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif return 0; } #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; struct am335x_baseboard_id header; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* Now set variables based on the header. */ strncpy(safe_string, (char *)header.name, sizeof(header.name)); safe_string[sizeof(header.name)] = 0; setenv("board_name", safe_string); strncpy(safe_string, (char *)header.version, sizeof(header.version)); safe_string[sizeof(header.version)] = 0; setenv("board_rev", safe_string); #endif return 0; } #endif #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 1, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 1, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; #endif /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr * in the environment * Perform fixups to the PHY present on certain boards. We only need this * function in: * - SPL with either CPSW or USB ethernet support * - Full U-Boot, with either CPSW or USB ethernet * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ && defined(CONFIG_SPL_BUILD)) || \ ((defined(CONFIG_DRIVER_TI_CPSW) || \ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* * * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device in U-Boot, we only do this for the first instance. */ #define AR8051_PHY_DEBUG_ADDR_REG 0x1d #define AR8051_PHY_DEBUG_DATA_REG 0x1e #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, AR8051_DEBUG_RGMII_CLK_DLY_REG); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY); } #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; } #endif
Sir,
These are the modifications i made according to my customised board.