Linux: McASP3 Testing

Hi Pavel,

I tried to modify the dts similar to DRA72 DTS file. I have attached the dts file. Please check I am getting the below error :

2543.DTS.txt

[    1.762663] clk: failed to reparent atl_clkin2_ck to dpll_abe_m2_ck: -22

[    1.771629] dra7-atl: probe of 4843c000.atl failed with error -22

Best Regards,

Ganesh

Ganesh Tenka said:

[    1.762663] clk: failed to reparent atl_clkin2_ck to dpll_abe_m2_ck: -22

This line (from your DTS.txt) looks suspicious:

&mcasp3 {

fck_parent = "atl_clkin2_ck";

}

In AM572x EVM we have:

&mcasp3 {

assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&sys_clkin2>;

}

This means we set bits CM_L4PER2_MCASP3_CLKCTRL[23:22] CLKSEL_AHCLKX = 0x7: Selects SYS_CLK2


In DRA72x EVM we have:

&mcasp3 {

    assigned-clocks = <&mcasp3_ahclkx_mux>;
    assigned-clock-parents = <&atl_clkin2_ck>;

}

This means we set bits CM_L4PER2_MCASP3_CLKCTRL[23:22] CLKSEL_AHCLKX = 0x4: Selects ATL CLK2

What is your idea regarding McASP3 ahclkx clock source? The available options are selected in CLKSEL_AHCLKX bits.

Regards,
Pavel

Hi Pavel,

Since I have to do according to dra72, I have added the below lines in my dts ,

&atl {
status = "okay";

assigned-clocks = <&atl_clkin2_ck>;
assigned-clock-parents = <&dpll_abe_m2_ck>;
assigned-clock-rates = <5644800>;

atl2 {
aws = <DRA7_ATL_WS_MCASP3_FSX>; /*Mux mode 4*/
};
};

&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

Still I am getting this error,

[ 1.774577] clk: failed to reparent atl_clkin2_ck to dpll_abe_m2_ck: -22
[ 1.781419] dra7-atl: probe of 4843c000.atl failed with error -22

Because of this clock not configured, I am getting this:

root@am57xx-evm:~# aplay audio.wav
[  317.325534] platform 4843c000.atl: atl2 has not been configured
audio.wav: No such file or directory



Best Regards,
Ganesh

Pavel,

In our custom board, except the clock to AIC3104 MCLK everything is same as AM572x only and ausio IC also changed.

Now I am getting the below errors. I am using TLV320AIC3104 audio IC

root@am57xx-evm:~# arecord -d 10 -f cd -t wav audio.wav                                                                                        

Recording WAVE 'audio.wav' : [   79.107645] tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121

Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

arecord: pcm_read:2039: read error: Input/output error

root@am57xx-evm:~# aplay audio.wav

Playing WAVE 'audio.wav' : [   94.597618] tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121

Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

4428.am57xx-beagle-x15.txt

2235.McASP3_Clock.txt

I suspect I2C interface not working. Or I am missing anything in dts file?

Best Regards,

Ganesh

Ganesh,

Ganesh Tenka said:

In our custom board, except the clock to AIC3104 MCLK everything is same as AM572x only and ausio IC also changed.

What do you mean here? What changes you have in audio IC?

Ganesh Tenka said:

Recording WAVE 'audio.wav' : [   79.107645] tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121

Do you provide the MCLK to the audio IC (aic3104)? Make sure you have clock signal from pin B26 (mode mcasp3_ahclkx) to AIC3104 MCLK. You can check this with oscilloscope. Can you also provide me the value of CTRL_CORE_PAD_XREF_CLK2 register? You can take this with devmem2 tool from user space. Also ahclkx is not enabled at McASP level by default. Have you modified the Platform driver (sound/soc/davinci/davinci-mcasp.c) to enable this?

Regards,
Pavel

Ganesh,

Ganesh Tenka said:

root@am57xx-evm:~# devmem2 0x4A00369C
/dev/mem opened.
Memory mapped at address 0xb6fe0000.
Read at address 0x4A00369C (0xb6fe069c): 0x00010003

You have correct value in CTRL_CORE_PAD_XREF_CLK2 register.

Ganesh Tenka said:

In have seen in oscilloscope, I am not getting clock on B26. I have not modified anything in (sound/soc/davinci/davinci-mcasp.c) file.

You should enable AHCLKX output from the McASP3 module. This should be done in davinci-mcasp.c file. For more details see AM571x TRM, section 24.6.4.2.1 MCASP Transmit Clock

An internally generated high-frequency clock can be optionally driven out onto the AHCLKX pin for the Tx part to serve as a reference clock for other
components in the system.

Regards,
Pavel

Ganesh Tenka said:

But still not working.

Do you mean that you are still not getting clock signal on pin B26 (mode mcasp3_ahclkx)? And do you have clock signals on other McASP3 clock pins (aclkx, fsx)?

Can you provide me McASP3 module registers and McASP3 pinmux settings dump? You should get the values after aplay command is executed, with devmem2 tool.

Regards,
Pavel

Pavel,

I have test points to MCLK and AFSX. I am not getting anything on these two signals.

root@am57xx-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: BeagleBoardX15 [BeagleBoard-X15], device 0: davinci-mcasp.0-tlv320aic3x-hifi tlv320aic3x-hifi-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
root@am57xx-evm:~# arecord -d 10 -f cd -t wav audio.wav
Recording WAVE 'audio.wav' : [  179.927527] tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121
Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
arecord: pcm_read:2039: read error: Input/output error
root@am57xx-evm:~# aplay audio.wav
Playing WAVE 'audio.wav' : [  272.277579] tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121
Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

McASP3 signals:

root@am57xx-evm:~# devmem2 0x4A00369C
/dev/mem opened.
Memory mapped at address 0xb6fac000.
Read at address  0x4A00369C (0xb6fac69c): 0x00010003

root@am57xx-evm:~# devmem2 0x4A003724
/dev/mem opened.
Memory mapped at address 0xb6f59000.
Read at address  0x4A003724 (0xb6f59724): 0x00040000
root@am57xx-evm:~# devmem2 0x4A003728
/dev/mem opened.
Memory mapped at address 0xb6f21000.
Read at address  0x4A003728 (0xb6f21728): 0x00040000
root@am57xx-evm:~# devmem2 0x4A00372C
/dev/mem opened.
Memory mapped at address 0xb6fc8000.
Read at address  0x4A00372C (0xb6fc872c): 0x00040000
root@am57xx-evm:~# devmem2 0x4A003730
/dev/mem opened.
Memory mapped at address 0xb6f03000.
Read at address  0x4A003730 (0xb6f03730): 0x00040000

I think with devmem2 we cannot read the McASP3 registers, I am getting below errors.

root@am57xx-evm:~# devmem2 0x48468000
/dev/mem opened.[  476.766543] ------------[ cut here ]------------
[  476.772498] WARNING: CPU: 0 PID: 762 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x248/0x34c()
[  476.782019] 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Read): Data Access in User mode during Functional access
[  476.793629] Modules linked in: gdbserverproxy(O) cryptodev(O) cmemk(O) xhci_plat_hcd xhci_hcd usbcore dwc3 udc_core omapdrm_pvr(O) phy_omapn
[  476.821153] CPU: 0 PID: 762 Comm: devmem2 Tainted: G           O    4.1.13-g8dc6617 #38
[  476.829189] Hardware name: Generic DRA72X (Flattened Device Tree)
[  476.835308] Backtrace:
[  476.837780] [<c0013018>] (dump_backtrace) from [<c001323c>] (show_stack+0x18/0x1c)
[  476.845379]  r7:c030ff28 r6:00000093 r5:c08c990c r4:00000000
[  476.851101] [<c0013224>] (show_stack) from [<c0629240>] (dump_stack+0x9c/0xdc)
[  476.858359] [<c06291a4>] (dump_stack) from [<c0039748>] (warn_slowpath_common+0x88/0xb8)
[  476.866480]  r5:00000009 r4:dfd65e00
[  476.870088] [<c00396c0>] (warn_slowpath_common) from [<c00397b0>] (warn_slowpath_fmt+0x38/0x40)
[  476.878819]  r8:c07cf664 r7:00000002 r6:ee962610 r5:c07cf724 r4:c07cf7c8
[  476.885591] [<c003977c>] (warn_slowpath_fmt) from [<c030ff28>] (l3_interrupt_handler+0x248/0x34c)
[  476.894496]  r3:ee962480 r2:c07cf7c8
[  476.898098]  r4:80080003
[  476.900652] [<c030fce0>] (l3_interrupt_handler) from [<c0079ac4>] (handle_irq_event_percpu+0x80/0x13c)
[  476.909994]  r10:c08f2729 r9:ee947780 r8:00000017 r7:00000000 r6:00000000 r5:ee9477e0
[  476.917893]  r4:ee962980
[  476.920447] [<c0079a44>] (handle_irq_event_percpu) from [<c0079bc4>] (handle_irq_event+0x44/0x64)
[  476.929354]  r10:be8d2b14 r9:00000001 r8:ee806000 r7:00000000 r6:ee962980 r5:ee9477e0
[  476.937252]  r4:ee947780
[  476.939805] [<c0079b80>] (handle_irq_event) from [<c007c8f0>] (handle_fasteoi_irq+0xb8/0x17c)
[  476.948362]  r7:00000000 r6:c08b1a7c r5:ee9477e0 r4:ee947780
[  476.954077] [<c007c838>] (handle_fasteoi_irq) from [<c0079128>] (generic_handle_irq+0x34/0x44)
[  476.962721]  r7:00000000 r6:00000000 r5:00000017 r4:00000017
[  476.968438] [<c00790f4>] (generic_handle_irq) from [<c0079400>] (__handle_domain_irq+0x64/0xbc)
[  476.977171]  r5:00000017 r4:c08a6d2c
[  476.980778] [<c007939c>] (__handle_domain_irq) from [<c00094ac>] (gic_handle_irq+0x2c/0x64)
[  476.989161]  r9:00000001 r8:30c5387d r7:fa212000 r6:dfd65fb0 r5:c08ac950 r4:fa21200c
[  476.996979] [<c0009480>] (gic_handle_irq) from [<c062f168>] (__irq_usr+0x48/0x60)
[  477.004491] Exception stack(0xdfd65fb0 to 0xdfd65ff8)
[  477.009564] 5fa0:                                     b6fae960 00010320 b6fac6e8 0d696914
[  477.017777] 5fc0: 00000000 00020f5c b6fa0000 b6fa04c0 00000002 00000001 be8d2b14 b6faa000
[  477.025988] 5fe0: 00020f5c be8d2aa8 00010400 b6f90ad4 200b0030 ffffffff
[  477.032627]  r7:30c5387d r6:ffffffff r5:200b0030 r4:b6f90ad4
[  477.038337] ---[ end trace 05259e3cd2a6c788 ]---

Memory mapped at address 0xb6faa000.
[  477.043155] Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
[  477.053829] pgd = d5016d40
[  477.056545] [00000000] *pgd=ae3b7003, *pmd=adf0e003, *pte=00000000
Read at address  0x48468000 (0xb6faa000): 0x00000000
8713.DTS.txt

Best Regards,

Ganesh

Ganesh Tenka said:

I have test points to MCLK and AFSX. I am not getting anything on these two signals.

Do you mean you have test points on pins B26 (xref_clk2.mcasp3_ahclkx) and F15 (mcasp3_fsx.mcasp3_fsx)? Do you probe these signals during aplay/arecord execution?

Ganesh Tenka said:

I think with devmem2 we cannot read the McASP3 registers, I am getting below errors.

Can you dump the McASP3 registers at the end of the mcasp_start_rx() function at mcasp driver:

linux-kernel/sound/soc/davinci/davinci-mcasp.c

static void mcasp_start_rx(struct davinci_mcasp *mcasp)
{

......

/* enable receive IRQs */
    mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
               mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);

// add here McASP3 registers dump, McASP3 pinmux dump and CM_L4PER2_MCASP3_CLKCTRL


}

Then when you execute arecord command, you should get the correct values. In order to print these registers from the linux kernel, you should translate the physical address to virtual.

Regards,
Pavel

Pavel,


Do you mean you have test points on pins B26 (xref_clk2.mcasp3_ahclkx) and F15 (mcasp3_fsx.mcasp3_fsx)? Do you probe these signals during aplay/arecord execution?

Yes while execution I saw in the signals in CRO. Nothing is coming.


I tried to print the messages using the below code in

linux-kernel/sound/soc/davinci/davinci-mcasp.c

static void mcasp_start_rx(struct davinci_mcasp *mcasp)
{

I am getting kernel panic with the below code. I am not sure whether it correctly translates physical address to virtual address. Help me how to print the register values in kernel code, then I can share you the register values.



virt_addr = phys_to_virt(0x48468000);
printk(KERN_INFO "Virtual address is %x\n",virt_addr);
printk(KERN_INFO "virtual address is %x and value is %x\n",virt_addr,*virt_addr);



Best Regards,

Ganesh

Pavel,

Please find the register dump in the below file:

7824.McASP3 Registers.txt

Best Regards,

Ganesh

Ganesh,

Regarding McASP3 register dump, I see MCASP_PDIR/0x48468014 is 0x1, which is not correct. You have input (value of 0) set for bits [28]afsx, [27ahclkx and [26]aclkx.

Reg_address == 48468014 , value == 1 

Please add printk() functions in davinci-mcasp.c to see how the flow goes.

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
    struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    int ret = 0;
    u32 data_delay;
    bool fs_pol_rising;
    bool inv_fs = false;


+printk(Enter davinci_mcasp_set_dai_fmt()/n");

..............

switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
    case SND_SOC_DAIFMT_CBS_CFS:
        /* codec is clock and frame slave */

       +printk("case SND_SOC_DAIFMT_CBS_CFS/n");
        mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
        mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

        mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
        mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

        mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
        mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
        mcasp->bclk_master = 1;
        break;

.......

}

static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir)
{
    struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);

   +printk(Enter davinci_mcasp_set_sysclk()/n");

pm_runtime_get_sync(mcasp->dev);
    if (dir == SND_SOC_CLOCK_OUT) {

      +printk("dir == SND_SOC_CLOCK_OUT/n");
        mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
        mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
        mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);

.......

}

Hi Deep,

You can print the register dump, like below

  static void __iomem *mcasp3_base;
uint32_t value,ui_temp;

mcasp3_base = ioremap(0x4A009868 ,4);
value =  __raw_readl(mcasp3_base);     
printk(KERN_INFO "CM_L4PER2_MCASP3_CLKCTRL  %x\n",value);

Best Regards,

Ganesh

Thanks Ganesh,

I am also getting the same tlv320aic3x-codec 0-0018: Unable to sync registers 0x1-0x1. -121 error

I will try to add the register dump. In which function of mcasp-davinci.c you have added this? Please let me know

Thanks

Ganesh,

Ganesh Tenka said:

In boot log, I am getting like this,
[ 8.029371] aic_dvdd_fixed: supplied by vdd_3v3
[ 8.274890] Enter davinci_mcasp_set_sysclk()
[ 8.279211] dir == SND_SOC_CLOCK_OUT
[ 8.283462] Enter davinci_mcasp_set_dai_fmt()
[ 8.287919] case SND_SOC_DAIFMT_CBM_CFM
[ 8.292323] asoc-simple-card sound@0: tlv320aic3x-hifi <-> 48468000.mcasp mapping ok
[ 8.667313] ldo4: supplied by evm_3v3_sd

Modify mcasp driver like below:

case SND_SOC_DAIFMT_CBM_CFM:
        /* codec is clock and frame master */
        mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
        mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

        mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
        mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

        mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
                   ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);

Let me know the result.

Regards,
Pavel

Ganesh Tenka said:

I am getting MCLK, while executing aplay and arecord commands, MCLK = 20MHz I am getting.

So you finally have clock on the B26 pin (xref_clk2.mcasp3_ahclkx) supplying to AIC3x MCLK input, and it is 20MHz, is that correct?

Note that on the AM572x TI EVM we have 22.5792MHz clock to supply AIC3x MCLK input. I will check with the Audio Codec team if supplying 20MHz instead of 22.5792MHz will not cause any problem.

Ganesh Tenka said:

[ 392.850636] XREF_CLKOUT2 == 10003

Please try with bit [18] INPUTENABLE = 1, as below is what we have in AM571x TRM:

NOTE: For the mcaspx_aclkx, mcaspx_ahclkx and mcaspx_aclkr signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.

Regards,
Pavel

Pavel,

Values in
CM_L4PER2_MCASP3_CLKCTRL 2, [27:24] is 0 means 0x0: Selects ABE_24M_GFCLK

MCASP_AHCLKXCTL 188000, MCASP_AHCLKXCTL[15] = 1, 0x1: Internal transmit high-frequency clock source from output of
programmable high clock divider.

Please try with bit [18] INPUTENABLE = 1, as below is what we have in AM571x TRM:

NOTE: For the mcaspx_aclkx, mcaspx_ahclkx and mcaspx_aclkr signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.

18th bit of PAD config register is already enabled only.

[   24.393131] MCASP3_ACLKX == 40000
[   24.393131]  MCASP3_FSX == 40000
[   24.393131] MCASP3_AXR0 ==40000
[   24.393131] MCASP3_AXR1 == 40000




Best Regards,
Ganesh

Ganesh Tenka said:

CM_L4PER2_MCASP3_CLKCTRL 2, [27:24] is 0 means 0x0: Selects ABE_24M_GFCLK

can you try with CM_L4PER2_MCASP3_CLKCTRL[27:24] CLKSEL_AHCLKX = 0x7 (SYS_CLK2 comes from OSC1), what frequency you have than in MCLK pin input?

Ganesh Tenka said:

MCASP_AHCLKXCTL[15] = 1

Keep MCASP_AHCLKXCTL[15] = 1 for now

Ganesh Tenka said:

Please try with bit [18] INPUTENABLE = 1, as below is what we have in AM571x TRM:

NOTE: For the mcaspx_aclkx, mcaspx_ahclkx and mcaspx_aclkr signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.

18th bit of PAD config register is already enabled only.

[   24.393131] MCASP3_ACLKX == 40000
[   24.393131]  MCASP3_FSX == 40000
[   24.393131] MCASP3_AXR0 ==40000
[   24.393131] MCASP3_AXR1 == 40000

I do not get your point here. What you have modified regarding McASP3 pinmux and why?

What I suggest in that post was:

Modify XREF_CLKOUT2 bit [18] to 1, nothing more, nothing less.

I am afraid that when I suggest you to modify something specific, you do not modify that specific settings, but modify other settings, thus we are not close in resolving the issue.

Regards,
Pavel

Ganesh,

Ganesh Tenka said:

[ 29.557849] CM_L4PER2_MCASP3_CLKCTRL 7000002

Looks correct.

Ganesh Tenka said:

[ 29.562225] MCASP_AHCLKXCTL 188000

Can you try with MCASP_AHCLKXCTL[15] HCLKXM = 0? What frequency you have in this case? To set DAVINCI_MCASP_AHCLKXCTL_REG [15] AHCLKXE to 1, you need to modify davinci-mcasp.c driver, davinci_mcasp_set_sysclk() function

Ganesh Tenka said:

Means CLKSEL_AHCLKX = 0x7 , and MCLK we are getting as 180.63MHz, multiple of 22.5792, somewhere may be it is multiplied by 8 it seems.

So with CLKSEL_AHCLKX = 0x0 you have 20MHz on the mcasp3_ahclkx pin output, and with CLKSEL_AHCLKX = 0x7 you have 180.63MHz on the mcasp3_ahclkx pin output?

This 180.63MHz frequency looks suspicious, can you double check? In AM571x DM (Table 7-48. Timing Requirements for McASP3), the min cycle time for AHCLKX is 20ns, which corresponds to max frequency of 50MHz, while you have 180.63MHz there.

Regards,
Pavel

Hi Pavel,

We have added following as per your suggestion,

&mcasp3 {

#sound-dai-cells = <0>;

status = "okay";

pinctrl-0 = <&mcasp3_pins_default>;

assigned-clocks = <&mcasp3_ahclkx_mux>;

+assigned-clock-parents = <&sys_clkin2>;

......

}

&atl {

        pinctrl-names = "default";

        pinctrl-0 = <&atl_pins>;

        assigned-clocks = <&abe_dpll_sys_clk_mux>,

                          <&atl_gfclk_mux>,

                          <&dpll_abe_ck>,

                          <&dpll_abe_m2x2_ck>,

                          <&atl_clkin2_ck>;

        assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;

        assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

        status = "okay";

        atl2 {

                bws = <DRA7_ATL_WS_MCASP2_FSX>;

                aws = <DRA7_ATL_WS_MCASP3_FSX>;

        };

};

we have added atl node, after that we are getting 180.6336MHz. Later we changed to 22579200 then we are getting 22.5792MHz.

Now also we are facing unable to sync registers error when we run arecord command.Kindly suggest what are other things we missed.

Thanks & Regards,

N.V.Subbaiah

Subbaiah,

nallapaneni venkata subbaiah said:

&atl {

        pinctrl-names = "default";

        pinctrl-0 = <&atl_pins>;

        assigned-clocks = <&abe_dpll_sys_clk_mux>,

                          <&atl_gfclk_mux>,

                          <&dpll_abe_ck>,

                          <&dpll_abe_m2x2_ck>,

                          <&atl_clkin2_ck>;

        assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;

        assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

        status = "okay";

        atl2 {

                bws = <DRA7_ATL_WS_MCASP2_FSX>;

                aws = <DRA7_ATL_WS_MCASP3_FSX>;

        };

We do not have ATL module in AM571x device, please remove any reference of ATL in your DTS

nallapaneni venkata subbaiah said:

&mcasp3 {

#sound-dai-cells = <0>;

status = "okay";

pinctrl-0 = <&mcasp3_pins_default>;

assigned-clocks = <&mcasp3_ahclkx_mux>;

+assigned-clock-parents = <&sys_clkin2>;

......

}

Update as below and try again:

assigned-clocks = <&mcasp3_ahclkx_mux>;

+assigned-clock-parents = <&sys_clkin2>;

+assigned-clock-rates = <22579200>;

Ganesh Tenka said:

Updated as below and tried:

assigned-clocks = <&mcasp3_ahclkx_mux>;

+assigned-clock-parents = <&sys_clkin2>;

+assigned-clock-rates = <22579200>;


MCLK was still 20MHz.

So you have the below setup?

CM_L4PER2_MCASP3_CLKCTRL[27:24] CLKSEL_AHCLKX = 0x7 (SYS_CLK2)

MCASP_AHCLKXCTL[15] HCLKXM = 1 (internal AHCLKX)

MCASP_PDIR[27] AHCLKX = 1 (output)

With this setup you have 20MHz on the AIC3x MCLK, correct? Seems we have the below flow with this setup:

OSC0 (20MHz) -> ABE_DPLL -> AUXCLK -> McASP3 -> mcasp3_ahclkx -> AIC3x MCLK

Ganesh Tenka said:

If the frequency of MCLK is still 20MHz (not 22.5792MHz), proceed to the below modification. In davinci-mcasp.c driver, change DAVINCI_MCASP_AHCLKXCTL_REG[15] AHCLKXE from 1 to 0 and check again the MCLK frequency.

MCLK = 20 MHz.

So you have the below setup?

CM_L4PER2_MCASP3_CLKCTRL[27:24] CLKSEL_AHCLKX = 0x7 (SYS_CLK2)

MCASP_AHCLKXCTL[15] HCLKXM = 0 (external AHCLKX)

MCASP_PDIR[27] AHCLKX = 1 (output)

With this setup you have 20MHz on the AIC3x MCLK, correct?

Ganesh Tenka said:

If the frequency of MCLK is still 20MHz (not 22.5792MHz), proceed to the below modification. In davinci-mcasp.c driver, change DAVINCI_MCASP_PDIR_REG[27] AHCLKX from 1 to 0 and check again the MCLK frequency.

MCLK = 0.

Please switch back MCASP_PDIR[27] AHCLKX = 1 (output)

Regards,
Pavel

Pavel,

With inclusion of atl node mentioned earlier, I am getting MCLK = 22.5792MHz, and the register values are same as per your suggestion.

Select SYS_CLK2 as input to ABE_PLL
· CM_CLKSEL_ABE_PLL_SYS[0] CLKSEL = 0x1
· CM_CLKSEL_ABE_PLL_REF[0] CLKSEL = 0x0

Select PER_ABE_X1_GFCLK as source for MCASP3_AUX_GFCLK
· CM_L4PER2_MCASP3_CLKCTRL[23:22] CLKSEL_AUX_CLK = 0x0

root@am57xx-evm:~# devmem2 0x4AE06118
/dev/mem opened.
Memory mapped at address 0xb6fdc000.
Read at address  0x4AE06118 (0xb6fdc118): 0x00000001
root@am57xx-evm:~# devmem2 0x4AE06108
/dev/mem opened.
Memory mapped at address 0xb6fc5000.
Read at address  0x4AE06108 (0xb6fc5108): 0x00000000
root@am57xx-evm:~# devmem2 0x4A009868
/dev/mem opened.
Memory mapped at address 0xb6f81000.
Read at address  0x4A009868 (0xb6f81868): 0x07030000
root@am57xx-evm:~#

But no change with the log, still getting pcm_read:2039: read error: Input/output error

Please find the log,

2746.Board_Log.txt

Regards,

Ganesh