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DM6467TZUT1 1080P60fps output underflow

customer ZTE use 1080P60fps input and output, do 1080P30fps encode + decode, then VP output underflow result in output image twinkle, VP 0/1 SCR priority all set as 1, highest among all master. Then we did some expriments result for comparison as below:

Input 1080P30fps, 1080P30fps encode+decode, 1080P60fps output, output image twikle.

Input 1080P60fps, 1080P30fps encode+decode, 1080P30fps output, output doesn't twinle.

System relative configurations as below:

VP 0/1 SCR priority = 1, TC0=2, TC1/2/3= 4, VDCE priority = 4.

DBS = 32byte, we tried with 64byte, output even worse.

DDR PBBPR = 0x10 get best performance.

VP DMA_SIZE= 128bytes get best performance.

My questions are:

 1. Why input 1080P60fps, output 1080P30fps doesn't twinkle, but vice verse input 1080P30fps, output 1080P60fps twinkle?

 2. Why VP SCR priority  is highest, it can't get prioritied service off DDR?

 3. VP0 and VP1 share SCR5 in front of SCR1, not connect to SCR1 directly, how does the SCR priority work, in round robin between same level priority? we found SCR priority setting VP0=2, VP1=1 lead to worse twinkling. Why VP0 priority impacted VP1 priority?

 4. DDR PBBPR value specify the number of memory transfers to elevate the oldest command in FIFO, how many memory transfers of the oldest command will be serviced before it hand over to next command? Who is the next command: the new oldest command? or highest priority command will be serviced? if the next command is the highest priority command, then why VP still underflow?

5. How to gurantee VP1(output) get highest piority of DDR BW? Decrease DBS(TC EDMAburst size)? increase VP DMA_SIZE? but VP only have 512byte ping-pong buffer, it is much less than that of DM642.

6. We can ignore the realtime of encoding/decoding, but need to gurantee VP output doesn't twinkle, how to configure it?

We also did experiment to separte VP and encode/decode, VP input 1080P60fps to fix address buffer, VP output 1080P60 from fix address buffer, doing dummy EDMA transfer on TC, TC priority is 2, VP priority is 1:

when only use 1 TC, EDMA throughput is 822Mbyte *2=~1.6Gbyte/s, output doesn't twinkle.

When use 2 TC, EDMA throughput also is about ~1.6Gbyte, output twinkle

When use 3, or 4 TC, EDMA throughput is similar, output twinkle worse.

Why with same throughtput, use 1 TC, output doesn't twinkle? but use >= 2 TC, output twinkle? and more TC, twinkle worse.

Compared with Encode/decode DDR BW, it is less than 1.6Gbyte/s, So the issue seems relate to the number of TC used?