Hi,
I'm having problem running HEVC 2.0.0.0 on multiple DSPs (16 cores). Memory block is corrupted(zeroized) inside process call on first core (i.e. DSP#0 core#0).
In my configuration block of DDR3 memmory 85000000 - 86000000 is configured in app.cfg as SharedRegion (with HeapMemMP) of uncached DDR3 memory. I allocate from it when DDR3 uncached is required.
I create mailbox structure in DDR3 uncached memory. It is created by address @85001d00 in logs.
Before process call on core#0 mailbox structure is correct:
process inputID=1 outBuf=@6488c2b8
mailbox handle=@85001d00 sender=1 states=@64870d08 data=@64873be8
then I print again content of mailbox structure in first barrWait callback (H265Ebarrier4 cross DSP barrier):
barrWait h=@0084e4d8 v=@64870c98 mailbox handle=@85001d00 sender=0 states=@00000000 data=@00000000
and mailbox structure is already zeroized.
Other information:
1) This doesn't happens with HEVC 1.0.0.44 running on the same code base.
2) I checked memory allocations and see that allocated memory blocks do not overlap. You can also see this in keyCreate logs.
3) I do not call process on slave cores (I replaced it with while(1); ) so I know that it is master core modifies memory
4) On DSP#1 core#0 (user_id=8) the behaviour is the same. Eventually the mailbox is located by the same address @85001d00 and is zeroized too in the same way as on DSP#0 core#0 (user_id=0).
5) There are no other multicore API callbacks before first barrWait.
6) Right before mailbox other shm buffers are allocated (you can see it in logs):
name=shared_mem_local_str00 address=@85000a80 size=448
name=shared_mem_SFRC_State00 address=@85000c80 size=1272
name=shared_mem_STM00 address=@85001180 size=2886
If i allocate additional 10KiB buffer that is placed between DDR3 uncached shms and mailbox stucture the maibox data is not zeroized.
Most likely zeroizing of the buffers in process call goes out of bounds of requested shm blocks and touches mailbox data in my case.
Can you please check this?
Logs: 6443.memory_zero.zip
Regards,
Andrey Lisnevich
