HEVC encoder stuck on two chips mode

Marvin Liang

Other Parts Discussed in Thread: SYSBIOS

My customer met an issue when run the HEVC encoder on two chips mode, single chip is fine. DSP procedure use sv04 framework, but the encoder will stuck on process() API when encode the first frame.

After add some printf/log in both siuVidMc3LockAcquire and siuVidMc3LockRelease, we found that these functions will be called constantly. Please refer to attached log.

dsp_prt.log

Below are the changes which made different comparing to the official release sv04:

1) c2c memory map on these two C6678:

siuVidMc3_set_C2C_mapping(1, (XDAS_Void*)0x2620000, 0, (XDAS_Void*)0x62020000, 0x1000);
siuVidMc3_set_C2C_mapping(1, (XDAS_Void*)0x2620000, 0, (XDAS_Void*)0x62820000, 0x1000);
siuVidMc3_set_C2C_mapping(1, (XDAS_Void*)0x81E00000, 0, (XDAS_Void*)0x63000000, 16<<20);
siuVidMc3_set_C2C_mapping(1, (XDAS_Void*)0x81E00000, 0, (XDAS_Void*)0x64000000, 8<<20);

siuVidMc3_set_C2C_mapping(0, (XDAS_Void*)0x2620000, 1, (XDAS_Void*)0x62020000, 0x1000);
siuVidMc3_set_C2C_mapping(0, (XDAS_Void*)0x2620000, 1, (XDAS_Void*)0x62820000, 0x1000);
siuVidMc3_set_C2C_mapping(0, (XDAS_Void*)0x81E00000, 1, (XDAS_Void*)0x63000000, 16<<20);
siuVidMc3_set_C2C_mapping(0, (XDAS_Void*)0x81E00000, 1, (XDAS_Void*)0x64000000, 8<<20);

memory mapping should be fine which proved by simple writing test.

2) Below segment in original link.cmd of sv04 has been deleted since the customer designed a simple communication mechanism which proved in single chip.

MAILBOX_DSP_TO_HOST : origin = 0x80000000, length = 0x00180000
MAILBOX_HOST_TO_DSP : origin = 0x80180000, length = 0x00180000

Would you please answer below questions:

1. Why siuVidMc3LockAcquire and siuVidMc3LockRelease called constantly when encoder stuck in process()? Any clue to solve the issue?

2. From the code siuVctReceiveInput()@ siu\vct\SiuVctRun.c ,loos only core 0 have valid input parameter (if(node_id == CORE_TEAM_MAPPING[0]))
other slavecores have below
rxMsgPayload->msgId = HOST2DSP_MEDIA_PROCESS_REQ;
rxMsgPayload->u.process.inBufPtr[0] = NULL;
rxMsgPayload->u.process.inBufSize[0] = 0;
rxMsgPayload->u.process.outBufPtr[0] = NULL;
rxMsgPayload->u.process.inputId = 0xFFFFFFFF;
how do these slave cores get yuv data？ Does this information pass by tTaskParam.algInArgs.inputBufs = (XDAS_Int8 **)&sharedInputBufPtrX86[0]? If that, how to pass the sharedInputBufPtrX86[0] to the slave cores?

over 9 years ago

0 Palachandra Venkataraju over 9 years ago

Expert 1230 points

Hi Marvin Liang,

1. siuVidMc3LockAcquire and siuVidMc3LockRelease called constantly when encoder stuck in process

- To dig more into the issue can you please give information regarding HEVC Encoder Library Version, encoder config parameters and address and size of shared memory with respect to key index.

2. Access YUV data by slave cores

- Host copies yuv data to local DDR of each chip, yuv is visible to all the cores.

3. Deletion of MAILBOX_DSP_TO_HOST and MAILBOX_HOST_TO_DSP segment

- It looks like Host to DSP communication has been disabled, can you please share information regarding how host functionality (like copying of input to shared DDR) is managed.

Thanks and Regards,

Palachandra M V

0 Marvin Liang over 9 years ago in reply to Palachandra Venkataraju

TI__Expert 3015 points

Palachandra,

Please check below information.

Software version:

Source code development from mcsdk_video_2_2_0_42

encoder library C66x_h265venc_01_00_00_44_ELF

Summary for all the changes between MCSDK video FW and customer’s FW

Hardware： HOST is ARM CPU, EPs are 1xNetra and 2xC6678

Software:

HOST：

1）HOST does not use the cmem module, but also provide a 16MB physically contiguous chunk of the HOST DDR to Eps which can be accessed by 0x60000000

2）removed the mailbox mechanism, provide a simple messageQ mechanism through 0x60000000 PCIe space to communication with core0 ONLY. HOST can only have communication with core0 (the first core in the first chip), even the core8 is the core0 of the second chip, it can not communicate with HOST.

3）HOST PCIe driver is different with MCSDK_video, but similar. It configures the IB OB registers, guarantee the mapping between DSP and HOST is correct. Also this mapping has been set to DSPs by siuVidMc3_set_C2C_mapping(). Additional memory test proved the driver works fine.

DSP：

1 ： refer to sv04 FW，removed neu ，tsu modules， encoder use ENC_XDM_2_0 interface.

2 ： memory map change

1） Removed

MAILBOX_DSP_TO_HOST : origin = 0x80000000, length = 0x00180000

MAILBOX_HOST_TO_DSP : origin = 0x80180000, length = 0x00180000

Since the mailbox mechanism removed, the corresponding memory definition has been removed from the link.cmd. HOST provided 16MB physically contiguous chunk of DDR as inbound space, each DSP mapping this 16MB by 0x60000000. HOST and DSP can exchange message and YUV data through this memory window.

In two chip encoder mode, host only send message to core0 (core 0~ core15). When all 16 cores start up，all cores will call create encoder ， and succeed. Then only core0 is polling the messageQ from HOST, other cores are call xdm2p0_vid_enc_process() and block to a Barr. When core0 got the YUV data, YUV address will be transfer to core’s encoder parameter. The YUV address is outbound address of DSP, in other word, DSP use the HOST DDR directly.

There is no HOST operation to copy the YUV data to each chip’s local DDR in customer’s FW. And we have not found the corresponding code in MCSDK_video. Would this mechanism cause the stuck? If so, would you please guide us for this reference code in MCSDK_Video or explain how each chip use the YUV in local DDR?

2）

MAILBOX_CHIP2CHIP_RX : origin = 0x81E00000, length = 0x00200000

CHIP2CHIP_XFER : origin = 0x82000000, length = 0x00E00000

HOST_MANAGED_MEM : origin = 0x82E00000, length = 0x01000000

0x81E00000 ~0x83E00000 32MB is the 1st inbound of DSP，MAILBOX_CHIP2CHIP_RX and CHIP2CHIP_XFER usage is the same as the demo.

0x82E00000 can be read by another EP，currently this segment reserved for decoder， The decoded YUV will put to this space, another EP will read data from here through PCIe

configure 4KB inbound space to map IPC registers

3）

IPC_CHIP2CHIP_MAPPING : origin = 0x62000000, length = 0x01000000

MAILBOX_CHIP2CHIP_TX_1 : origin = 0x63000000, length = 0x00200000

CHIP2CHIP_XFER_PREV_CHIP : origin = 0x63200000, length = 0x00E00000

MAILBOX_CHIP2CHIP_TX_2 : origin = 0x64000000, length = 0x00200000

X86_CODEC_SHM : origin = 0x61000000, length = 0x01000000 //used for rc share to mc3

above memory maps are different with the original sv04, but the usages are the same.

3: Reserved INT No.14 for H265VENC_TI_IRES of siuCodecIsr. Removed INT No.15 of TIMER_8, it should be statistics related. When H265VENC_TI_IRES will be called in the encoder? Could the encoder be stuck by incorrect INT No.14 configuration?

Best Regards.

Marvin

0 Palachandra Venkataraju over 9 years ago in reply to Marvin Liang

Expert 1230 points

Hi Marvin

1. Since there exists a DSP Mapping of 16 MB space, can you please check if input yuv data is reflected at core 8 (core 0 of 2nd chip) before process call. If it is reflected then it looks fine. In MCSDK, Input YUV is copied to local DDR Memory in function module

int32_t DeviceIOTxSendFrame(DeviceIOInst_t *inst, DeviceIODesc_t *inputDesc, DeviceIODesc_t *outputDesc)

2. Ideally, even if data is not copied to individual chip DDR memory, it should not result in hang.

To check the reason for hang, can you please share us the

- Encoder config parameters, (such as Input Width, Input height, Qp ...) So that we can check at our end.

- Address and Size of shared memory with respect to key index. (Such as shared_mem_pcontext, shared_mem_bitconsumed ...) Allocated using function pointers keyCreate and shmMap, which will be helpful for debugging.

3. We need to analyze whether reserving/removing interrupt has any impact on encoder behavior.

Thanks and Regards,
Palachandra M V

0 Marvin Liang over 9 years ago in reply to Palachandra Venkataraju

TI__Expert 3015 points

Palachandra,

1. Encoder config parameter please refer to encparam.txt

encparam.txt

		//StaticParams - IVIDENC2_Params
		pStaticEnc->videnc2Params.size							= sizeof(IH265VENC_Params);
		pStaticEnc->videnc2Params.encodingPreset                = 4; // 0: DEFAULT, 1: HIGH_QUALITY, 2: HIGH_SPEED, 3: USER_DEFINED. If not USER_DEFINED most of configuration parameters are chosen by encoder, thus ignored.
		pStaticEnc->videnc2Params.rateControlPreset             = 2; // 1: LOW_DELAY,  2: STORAGE, 4: NONE,  5: USER_DEFINED
		pStaticEnc->videnc2Params.maxWidth                      = 1920;
		pStaticEnc->videnc2Params.maxHeight                     = 1080;
		pStaticEnc->videnc2Params.dataEndianness                = XDM_BYTE; // Not configurable
		pStaticEnc->videnc2Params.maxInterFrameInterval         = 1; // Max I to P frame distance. 1: no B frames, 2: one B frame, 3: two B frames, etc [1, 255]
		pStaticEnc->videnc2Params.maxBitRate                    = 2048*1200; // In bits per second. Should be valid as per LEVEL limit
		pStaticEnc->videnc2Params.minBitRate                    = 2048*1024; // In bits per second
		pStaticEnc->videnc2Params.inputChromaFormat             = XDM_YUV_420P; // Not configurable
		pStaticEnc->videnc2Params.inputContentType              = IVIDEO_PROGRESSIVE; // 0: PROGRESSIVE, 1: INTERLACED
		pStaticEnc->videnc2Params.operatingMode                 = IVIDEO_ENCODE_ONLY; // Not configurable
		pStaticEnc->videnc2Params.profile                       = IH265_MAIN_PROFILE; // TODO: change description
		pStaticEnc->videnc2Params.level                         = IH265_LEVEL_41; // TODO: change description
		pStaticEnc->videnc2Params.inputDataMode                 = IVIDEO_ENTIREFRAME; // Not configurable
		pStaticEnc->videnc2Params.outputDataMode                = IVIDEO_ENTIREFRAME; // Not configurable
		pStaticEnc->videnc2Params.numInputDataUnits             = 1;
		pStaticEnc->videnc2Params.numOutputDataUnits            = 1;

		int i;
		for (i = 0 ; i < IVIDEO_MAX_NUM_METADATA_PLANES; i++) 
		{
			pStaticEnc->videnc2Params.metadataType[i] = IVIDEO_METADATAPLANE_NONE;
		}

		//StaticParams - Misc
		pStaticEnc->scalingMatrixPreset		= IH265_SCALINGMATRIXPRESET_DEFAULT;
		pStaticEnc->decRefreshType			= 0; // Decoder referesh type: IDR or CDR [0 or 1].
		pStaticEnc->decRefreshInterval		= 0;
		pStaticEnc->enableTransQuantBypass	= 0;
		pStaticEnc->maxPoc					= 256;
		pStaticEnc->enableTransformSkip		= 0;
		pStaticEnc->maxIntraFrameInterval	= 10000;
		pStaticEnc->enableWPP				= 1;
		pStaticEnc->maxNumRefFrames			= 1;
		pStaticEnc->enableVirtualTile		= 31;
		pStaticEnc->disableVirtualTileDependency = 0;
		pStaticEnc->debugTraceLevel			= 0;
		pStaticEnc->lastNFramesToLog		= 0;

		//StaticParams - IH265VENC_RateControlParams
		pStaticEnc->rateControlParams.rateControlParamsPreset	= IH265_RATECONTROLPARAMS_USERDEFINED;
		pStaticEnc->rateControlParams.rcAlgo					= IH265_RATECONTROL_CBR;
		pStaticEnc->rateControlParams.qpI						= 28;
		pStaticEnc->rateControlParams.qpMaxI					= 50;
		pStaticEnc->rateControlParams.qpMinI					= 10;
		pStaticEnc->rateControlParams.qpP						= 28;
		pStaticEnc->rateControlParams.qpMaxP					= 50;
		pStaticEnc->rateControlParams.qpMinP					= 10;
		pStaticEnc->rateControlParams.qpOffsetB					= 4;
		pStaticEnc->rateControlParams.qpMaxB					= 50;
		pStaticEnc->rateControlParams.qpMinB					= 10;
		pStaticEnc->rateControlParams.enableFrameSkip			= 0;
		pStaticEnc->rateControlParams.enablePartialFrameSkip	= 0;
		pStaticEnc->rateControlParams.qualityFactorIP			= 0;
		pStaticEnc->rateControlParams.cbQPIndexOffset			= 2;
		pStaticEnc->rateControlParams.crQPIndexOffset			= 2;
		pStaticEnc->rateControlParams.initialBufferLevel		= 2000000;
		pStaticEnc->rateControlParams.hrdBufferSize				= 2000000;
		pStaticEnc->rateControlParams.enableHRDComplianceMode	= 0;
		pStaticEnc->rateControlParams.maxFrameSkipCnt			= 0;
		pStaticEnc->rateControlParams.SubFrameRC				= 0;
		pStaticEnc->rateControlParams.maxDeltaQP				= 0;
		pStaticEnc->rateControlParams.enablePRC					= 0;

		//StaticParams - IH265VENC_LoopFilterParams
		pStaticEnc->loopFilterParams.loopFilterParamsPreset		= IH265_SLICECODINGPRESET_USERDEFINED;
		pStaticEnc->loopFilterParams.enableDeblockFilter		= 1;
		pStaticEnc->loopFilterParams.enableSaoFilter			= 1;// sao quality better
		pStaticEnc->loopFilterParams.enableLoopFilterSliceBoundary = 0;
		pStaticEnc->loopFilterParams.enableLoopFilterTileBoundary = 0;
		pStaticEnc->loopFilterParams.separateCbCrSAO = 0;
		pStaticEnc->loopFilterParams.offsetLoopFilterInPPSFlag	= 0;
		pStaticEnc->loopFilterParams.offsetDeblockBetaDiv2		= 0;
		pStaticEnc->loopFilterParams.offsetDeblockTcDiv2		= 0;

		//StaticParams - IH265VENC_GopCntrlParams
		pStaticEnc->gopCntrlParams.gopCntrlParamsPreset			= IH265_GOPCTRLPRESET_DEFAULT;

		//StaticParams - IH265VENC_SliceCodingParams
		pStaticEnc->sliceCodingParams.sliceCodingPreset			= IH265_SLICECODINGPRESET_USERDEFINED;
		pStaticEnc->sliceCodingParams.sliceCodingMode			= 0;
		pStaticEnc->sliceCodingParams.sliceCodingArg			= 0;
		pStaticEnc->sliceCodingParams.enableTiles				= 0;
		pStaticEnc->sliceCodingParams.numTileColumns			= 2;
		pStaticEnc->sliceCodingParams.numTileRows				= 2;
		pStaticEnc->sliceCodingParams.enableDependentSlice		= 0;

		//StaticParams - IH265VENC_IntraCodingParams
		pStaticEnc->intraCodingParams.intraCodingPreset			= IH265_INTRACODINGPRESET_USERDEFINED;
		pStaticEnc->intraCodingParams.intraRefreshMethod		= 0;
		pStaticEnc->intraCodingParams.intraRefreshRate			= 0;
		pStaticEnc->intraCodingParams.constrainedIntraPredEnable = 0;
		pStaticEnc->intraCodingParams.enableStrongIntraSmoothing = 1;
		pStaticEnc->intraCodingParams.matchYCbCrIntraMode		= 0;
		pStaticEnc->intraCodingParams.enableLumaIntra4x4Mode	= 0;
		pStaticEnc->intraCodingParams.enableLumaIntra8x8Mode	= 0;
		pStaticEnc->intraCodingParams.enableLumaIntra16x16Mode	= 0;
		pStaticEnc->intraCodingParams.enableLumaIntra32x32Mode	= 0;
		pStaticEnc->intraCodingParams.enableChromaIntra4x4Mode	= 0;
		pStaticEnc->intraCodingParams.enableChromaIntra8x8Mode	= 0;
		pStaticEnc->intraCodingParams.enableChromaIntra16x16Mode = 0;

		//StaticParams - IH265VENC_InterCodingParams
		pStaticEnc->interCodingParams.interCodingPreset			= IH265_INTERCODINGPRESET_USERDEFINED;
		pStaticEnc->interCodingParams.enableTmvp				= 0;
		pStaticEnc->interCodingParams.searchRangeHorP			= 144;
		pStaticEnc->interCodingParams.searchRangeVerP			= 32;
		pStaticEnc->interCodingParams.searchRangeHorB			= 144;
		pStaticEnc->interCodingParams.searchRangeVerB			= 32;
		pStaticEnc->interCodingParams.interCodingBias			= 0;
		pStaticEnc->interCodingParams.skipMVCodingBias			= 0;
		pStaticEnc->interCodingParams.numMergeCandidates		= 3;
		pStaticEnc->interCodingParams.enableBiPredMode			= 1;
		pStaticEnc->interCodingParams.enableFastIntraAlgo		= 1;

		//StaticParams - IH265VENC_VUICodingParams
		pStaticEnc->vuiCodingParams.vuiCodingPreset				= IH265_VUICODINGPRESET_DEFAULT;
		pStaticEnc->vuiCodingParams.aspectRatioInfoPresentFlag	= 0;
		pStaticEnc->vuiCodingParams.aspectRatioIdc				= 0;
		pStaticEnc->vuiCodingParams.videoSignalTypePresentFlag	= 0;
		pStaticEnc->vuiCodingParams.videoFormat					= 0;
		pStaticEnc->vuiCodingParams.videoFullRangeFlag			= 0;
		pStaticEnc->vuiCodingParams.colourDescriptionPresentFlag = 0;
		pStaticEnc->vuiCodingParams.colourPrimaries				= 0;
		pStaticEnc->vuiCodingParams.transferCharacteristics		= 0;
		pStaticEnc->vuiCodingParams.matrixCoefficients			= 0;
		pStaticEnc->vuiCodingParams.timingInfoPresentFlag		= 0;

		//StaticParams - IH265VENC_SEIParams
		pStaticEnc->seiParams.enableSeiFlag = 0;

		//StaticParams - IH265VENC_CTBCodingParams
		pStaticEnc->ctbCodingParams.maxCTBSize = 64;
		pStaticEnc->ctbCodingParams.maxCUDepth = 3;

			//DynamicParams - IVIDENC2_DynamicParams
			IH265VENC_DynamicParams* pDynEnc = (IH265VENC_DynamicParams*)pDynParam; 
			pDynEnc->videnc2DynamicParams.size				= sizeof(IH265VENC_DynamicParams);
			pDynEnc->videnc2DynamicParams.inputWidth		= 1920;
			pDynEnc->videnc2DynamicParams.inputHeight		= 1080;
			pDynEnc->videnc2DynamicParams.refFrameRate		= 30 * 1000;
			pDynEnc->videnc2DynamicParams.targetFrameRate	= 30 * 1000;
			pDynEnc->videnc2DynamicParams.targetBitRate		= 2048*1024;
			pDynEnc->videnc2DynamicParams.intraFrameInterval = 3000; // The number of frames between two I frames. 0: IPPPP..., 1: IIII..., 2: IPIPIPIPI, 3: IPPIPPIPPI or IPBIPBIPBI, etc.
			pDynEnc->videnc2DynamicParams.generateHeader	= XDM_ENCODE_AU; // 0: Encode entire access unit including headers, 1: Encode only header
			pDynEnc->videnc2DynamicParams.captureWidth		= 0;
			pDynEnc->videnc2DynamicParams.forceFrame		= IVIDEO_NA_FRAME; // -1: IVIDEO_NA_FRAME, 3: IVIDEO_IDR_FRAME
			pDynEnc->videnc2DynamicParams.interFrameInterval = 1; // I to P frame distance. 1: no B frames, 2: one B frame, 3: two B frames, etc [1, 255]
			pDynEnc->videnc2DynamicParams.mvAccuracy		= IVIDENC2_MOTIONVECTOR_QUARTERPEL; // Motion vectors accuracy. 0: integer pel., 2: quarter pel.
			pDynEnc->videnc2DynamicParams.sampleAspectRatioHeight	= 1;
			pDynEnc->videnc2DynamicParams.sampleAspectRatioWidth	= 1;
			pDynEnc->videnc2DynamicParams.ignoreOutbufSizeFlag = XDAS_FALSE; // Non configurable
			pDynEnc->videnc2DynamicParams.putDataFxn		= NULL;
			pDynEnc->videnc2DynamicParams.putDataHandle		= 0;
			pDynEnc->videnc2DynamicParams.getDataFxn		= NULL;
			pDynEnc->videnc2DynamicParams.getDataHandle		= 0;
			pDynEnc->videnc2DynamicParams.getBufferFxn		= NULL;
			pDynEnc->videnc2DynamicParams.getBufferHandle	= 0;
			pDynEnc->videnc2DynamicParams.lateAcquireArg	= 0;
			
			memcpy(&pDynEnc->rateControlParams, &pStaticEnc->rateControlParams, sizeof(pStaticEnc->rateControlParams));
			memcpy(&pDynEnc->loopFilterParams, &pStaticEnc->loopFilterParams, sizeof(pStaticEnc->loopFilterParams));
			memcpy(&pDynEnc->intraCodingParams, &pStaticEnc->intraCodingParams, sizeof(pStaticEnc->intraCodingParams));
			memcpy(&pDynEnc->interCodingParams, &pStaticEnc->interCodingParams, sizeof(pStaticEnc->interCodingParams));
			memcpy(&pDynEnc->ctbCodingParams, &pStaticEnc->ctbCodingParams, sizeof(pStaticEnc->ctbCodingParams));
			memcpy(&pDynEnc->sliceCodingParams, &pStaticEnc->sliceCodingParams, sizeof(pStaticEnc->sliceCodingParams));
			
			pDynEnc->enableTransQuantBypass = pStaticEnc->enableTransQuantBypass;
			pDynEnc->enableTransformSkip	= pStaticEnc->enableTransformSkip;
			pDynEnc->enableROI				= 0;

2. Key index related info please refer to keycreate.log. It is the output from keyCreate(), core0~core15 is encoder, core16~core23 is decoder.

keycreate.log

Best Regards.

Marvin

0 Kuladeepak Gowda over 9 years ago in reply to Marvin Liang

Intellectual 785 points

Hi Marvin Liang,
I have some queries about KeyCreate log,
1) Some of the shared allocation start addresses are same(shared_NAL_info_rmt,shared_mem_rmt_bitstream). Is this base address for allocation ?
2) Are you tring to encode in 2 chip or 3 chip ? Because allocation is happening for 24 cores.

Regards
Kuladeepak

0 Marvin Liang over 9 years ago in reply to Kuladeepak Gowda

TI__Expert 3015 points

Kuladeepak,

1) Sorry for the previous log is not clear. Attached is a new log.keycreate2.log

2) Yes, we are trying to encoder in 2 chip. I am not sure what do you mean Because allocation is happening for 24 cores. Would you please give us more detail regarding the allocation which you mentioned here?

Best Regards.

Marvin

0 Kuladeepak Gowda over 9 years ago in reply to Marvin Liang

Intellectual 785 points

Hi Marvin,

I didn't find any disturbance in the log. Previous KeyCreate log showed more then 16 core allocation, so I had a doubt on number of chip.

For present, we can go for tile based encoding where inter chip communication is minimal.

For Tile encoding,

enableTiles = 1

enableWPP = 0

Regards

Kuladeepak

0 Marvin Liang over 9 years ago in reply to Kuladeepak Gowda

TI__Expert 3015 points

Hi, Kuladeepak

Thanks a lot for your help. Now the two-chip encoder stuck issue looks solved with

enableTiles = 1

enableWPP = 0

But the performance is very low, even than single chip,100M cycles/frame. From these information, would you please give us more suggestion to find the root cause of encoder stuck and improve the performance?

Best Regards.

Marvin

0 snow wang over 8 years ago in reply to Marvin Liang

Prodigy 140 points

Is there any other expert to support this issue?@Kuladeepak,@Palachandra

Snow

0 Kuladeepak Gowda over 8 years ago in reply to Marvin Liang

Intellectual 785 points

Hi Marvin
Instead of Reserving INT No.14 for H265VENC_TI_IRES of siuCodecIsr, Can you try reserving H265VENC_TI_SchedulerISR.
If hang persistence, can you get the memory dump of memory which was allocated with "shared_mem_STM00/shared_mem_STM01" namestring.

Regards
Kuladeepak

0 Marvin Liang over 8 years ago in reply to Kuladeepak Gowda

TI__Expert 3015 points

Hi Kuladeepak,

1. Addtional, wee have added some log, found that actually the siuCodecIsr never has been called? Does it cause the hang?

reserving H265VENC_TI_SchedulerISR will met a DSP exception to the exception handler when creat the codec.

var EXCEPTION = xdc.useModule('ti.sysbios.family.c64p.Exception');
EXCEPTION.exceptionHook = "&custom_exception_handler";

[c6678 core 0] shared_mem_STM00 user_ID 0 num_users 8 handle addr 0x880ac280 shm.size 10212 shm.attr 4 , shm.alignment 128
[c6678 core 8] shared_mem_STM01 user_ID 8 num_users 8 handle addr 0x880ac280 shm.size 10212 shm.attr 4 , shm.alignment 128

Attached are the memory dump for 0x880ac280 on both chip 0 and chip 1.

shared_mem_STM00.zip shared_mem_STM01.zip

Thanks.

Marvin

0 Chris Meng over 8 years ago in reply to Marvin Liang

TI__Mastermind 35215 points

The hanging issue is fixed and it is due to not set C66 PCIe in supervisor mode

Processors

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HEVC encoder stuck on two chips mode