I use h264 encodec(H264FHDVENC.version.01.10.00.26.wizardversion.0.5.2), but only first frame is efficient in one GOP, another frame is empty?

Hi,

When I use this codec to encode 1080P, the X64P is generated successfully, but when I use it to encode, the result is: the first frame is good, but the size is a little large, another frame in this GOP is empty, the size is 12, such as in 30 frames, ths size is (108290, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12)

codec: H264FHDVENC.version.01.10.00.26.wizardversion.0.5.2

hdvicp: HDVICP.version.1.01.017

The Rule.mak is:

#
# This make variable must be set before the demos or examples
# can be built.  It must be set to either dm355, dm6446 or dm6467
#
PLATFORM=dm6467
ifndef PLATFORM
   $(error PLATFORM must be set in Rules.make to dm355,dm6467, or dm6446 before building the demos)
endif
HOME = /home/davinci
# The installation directory of the DVSDK  dvsdk_1_40_02_33.
DVSDK_INSTALL_DIR=${HOME}/dvsdk_1_40_02_33

# For backwards compatibility
DVEVM_INSTALL_DIR=$(DVSDK_INSTALL_DIR)

# Where the Davinci Multimedia Application Interface is installed
#DMAI_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/dmai_1_10_00_06
DMAI_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/dmai

# Where the Codec Engine package is installed.
CE_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/codec_engine_2_10_02

# Where the XDAIS package is installed.
XDAIS_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/xdais_6_10_01

# Where the DSP Link package is installed.
LINK_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/dsplink-davinci-v1.50-prebuilt

# Where the CMEM (contiguous memory allocator) package is installed.
CMEM_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/cmem_2_10
#CMEM_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/linuxutils_2_23_01

# Where the codec servers are installed (dm6446) or codecs (dm355)
ifneq ($(PLATFORM),dm355)
   CODEC_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/dm6467_dvsdk_combos_1_17
else
   CODEC_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/__CODEC_VERS__
endif

# Where the RTSC tools package is installed.
#XDC_INSTALL_DIR=${DVSDK_INSTALL_DIR}/xdctools_3_10_05_61
XDC_INSTALL_DIR=${DVSDK_INSTALL_DIR}/xdc_3_00_06

# Where Framework Components product is installed
#FC_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/framework_components_2_23_01
FC_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/framework_components_2_10_02

# Where DSP/BIOS is installed
BIOS_INSTALL_DIR=$(DVSDK_INSTALL_DIR)/

# The directory that points to your kernel source directory.
LINUXKERNEL_INSTALL_DIR=/opt/mv_pro_4.0.1/montavista/pro/devkit/lsp/ti-davinci/linux-2.6.10_mvl401_LSP_01_30_00_082

# The prefix to be added before the GNU compiler tools (optionally including
# path), i.e. "arm_v5t_le-" or "/opt/bin/arm_v5t_le-".
MVTOOL_DIR=/opt/mv_pro_4.0.1/montavista/pro/devkit/arm/v5t_le
MVTOOL_PREFIX=$(MVTOOL_DIR)/bin/arm_v5t_le-

# Where to copy the resulting executables and data to (when executing 'make
# install') in a proper file structure. This EXEC_DIR should either be visible
# from the target, or you will have to copy this (whole) directory onto the
# target filesystem.
EXEC_DIR=${HOME}/workdir/filesys/opt/dvsdk

The code server config file demo1080.cfg:

/* set up OSAL */
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;
osalGlobal.traceBufferSize = 0x40000;

/* configure default memory seg id to BIOS-defined "DDR" */
osalGlobal.defaultMemSegId = "DDR2";

/* Enable DSP-side BIOS logging */
var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');

/*
 *  ======== Server Configuration ========
 */
var Server = xdc.useModule('ti.sdo.ce.Server');
Server.threadAttrs.stackSize = 65536;
/*Server.threadAttrs.stackSize = 16384;*/
/*
 * The optional stack pad to add to non-configured stacks.  This is well
 * beyond most codec needs, but follows the approach of "start big and
 * safe, then optimize when things are working."
 */
Server.stackSizePad = 9000;

/* get various codec modules; i.e., implementation of codecs */
var H264ENC_1080P = xdc.useModule('ti.sdo.codecs.h264fhdvenc.ce.H264FHDVENC');
/*var HDVICP = xdc.useModule('ti.sdo.codecs.hdvicp.HDVICP');*/

/* Linking in the HDVICP Lib module  */
xdc.useModule('ti.sdo.codecs.hdvicp.HDVICP');

H264ENC_1080P.alg.codeSection  = "DDR2";
H264ENC_1080P.alg.intMemSection = "IRAM";

/* Switching off Outs Bufs Cache */
H264ENC_1080P.manageOutBufsCache = [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ];

Server.algs = [   
    {name: "h264enc_1080p", mod: H264ENC_1080P,groupId:0,threadAttrs: {
            stackMemId: 0, priority: Server.MINPRI + 1}
    },   
];

/*
 *  ======== DSKT2 and RMAN Configuration ========
 *  XDAIS Algorithm Memory and DMA allocation
 */
    var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
    DSKT2.DARAM0     = "IRAM";
    DSKT2.DARAM1     = "IRAM";
    DSKT2.DARAM2     = "IRAM";
    DSKT2.SARAM0     = "IRAM";
    DSKT2.SARAM1     = "IRAM";
    DSKT2.SARAM2     = "IRAM";
    DSKT2.ESDATA     = "DDRALGHEAP";
    DSKT2.IPROG      = "IRAM";
    DSKT2.EPROG      = "DDR2";
    DSKT2.DSKT2_HEAP = "DDR2";    /* to allocate internal DSKT2 object */
    /*DSKT2.trace = true;
    DSKT2.debug = true;*/
   
    DSKT2.ALLOW_EXTERNAL_SCRATCH = true;  
    DSKT2.DARAM_SCRATCH_SIZES = [ 65536, 0, 0,0,0,0,0, /* ... */ 0 ];
    DSKT2.SARAM_SCRATCH_SIZES = [ 65536, 0, 0,0,0,0,0, /* ... */ 0 ];
  
    var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
    RMAN.useDSKT2 = true;
    RMAN.tableSize = 10;
    RMAN.semCreateFxn = "Sem_create";
    RMAN.semDeleteFxn = "Sem_delete";
    RMAN.semPendFxn = "Sem_pend";
    RMAN.semPostFxn = "Sem_post";
    /*RMAN.debug = true;
    RMAN.trace = true;*/
   
    var EDMA3 = xdc.useModule('ti.sdo.fc.edma3.Settings');
   // EDMA3.globalInit = true;
    EDMA3.maxPaRams[0]           = 384;
    EDMA3.maxPaRams[1]           = 0;
    EDMA3.maxPaRams[2]           = 0;
    EDMA3.maxPaRams[3]           = 0;

    EDMA3.maxTccs[0]             = 49;
    EDMA3.maxTccs[1]             = 0;
    EDMA3.maxTccs[2]             = 0;
    EDMA3.maxTccs[3]             = 0;

    EDMA3.maxEdmaChannels[0]     = 49;
    EDMA3.maxEdmaChannels[1]     = 0;
    EDMA3.maxEdmaChannels[2]     = 0;
    EDMA3.maxEdmaChannels[3]     = 0;

    EDMA3.maxQdmaChannels[0] = 0;

    /*EDMA3.trace = true;
    EDMA3.debug = true; */  

    var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');
    /*EDMA3CHAN.debug = true;
    EDMA3CHAN.trace = true;*/

    var HDVICP =  xdc.useModule('ti.sdo.fc.ires.hdvicp.HDVICP');
    /*HDVICP.debug = true;
    HDVICP.trace = true;*/

    var HDINTC = xdc.useModule('ti.sdo.fc.hdintc.HDINTC');
    HDINTC.interruptVectorId_0 = 10;
    HDINTC.interruptVectorId_1 = 11;
    HDINTC.hdvicpInterruptEventNo_0 = 29;
    HDINTC.hdvicpInterruptEventNo_1 = 39;

    HDINTC.biosInterruptVectorId_0 = 7;
    HDINTC.biosInterruptVectorId_1 = 8;
    HDINTC.biosInterruptEventNo_0 = 30;
    HDINTC.biosInterruptEventNo_1 = 31;

The .tcf file, demo1080.tcf is:

/*
 * Setup platform-specific memory map, CLK rate, etc.
 */
var mem_ext = [
{
    comment:    "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
    name:       "DDRALGHEAP",
    base:       0x8BA00000,   // 186MB offset
    len:        0x04000000,   // 66MB  size
    space:      "code/data"
},
{
    comment:    "DDR2: off-chip memory for code and data",
    name:       "DDR2",
    base:       0x8FA00000,   // 250MB offset
    len:        0x00400000,   // 4MB   size
    space:      "code/data"
},
{
    comment:    "DSPLINK: off-chip memory for DSPLINK code and data",
    name:       "DSPLINKMEM",
    base:       0x8FE00000,   // 254MB offset
    len:        0x00100000,   // 1MB   size
    space:      "code/data"
},
{
    comment:    "RESET_VECTOR: off-chip memory for the reset vector table",
    name:       "RESET_VECTOR",
    base:       0x8FF00000,
    len:        0x00000080,
    space:      "code/data"
},
];

/* Specify the L2 memory setting */
var device_regs = {
    l1PMode: "32k",
    l1DMode: "32k",
    /*l2Mode: "64k"*/
    l2Mode: "64k"
};

var params = {
    clockRate: 594,
    catalogName: "ti.catalog.c6000",
    deviceName: "DM6467",
    regs: device_regs,
    mem: mem_ext
};

/*
 * Customize generic platform with parameters specified above.
 */
utils.loadPlatform("ti.platforms.generic", params);

/*  ===========================================================================
 *  Enable heaps and tasks
 *  ===========================================================================
 */
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);

/*  ===========================================================================
 *  Create heaps in memory segments that are to have heap
 *  ===========================================================================
 */
bios.DDR2.createHeap = true;
bios.DDR2.heapSize   = 0x00040000; // 256K

bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize   = bios.DDRALGHEAP.len;

/*  ===========================================================================
 *  GBL
 *  ===========================================================================
 */
prog.module("GBL").ENABLEALLTRC    = false;
prog.module("GBL").PROCID          = 0;

prog.module("GBL").C64PLUSCONFIGURE   = true ;
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;

/*  ===========================================================================
 *  HWI
 *  ===========================================================================
 */
bios.HWI_INT4.interruptSelectNumber = 16
bios.HWI_INT5.interruptSelectNumber = 17

/*  ===========================================================================
 *  MEM
 *  ===========================================================================
 */
prog.module("MEM").STACKSIZE = 0x1000 ;
prog.module("TSK").STACKSIZE = 0x1000 ;

/*  ===========================================================================
 *  Global Settings
 *  ===========================================================================
 */
prog.module("MEM").ARGSSIZE = 200;

/*  ===========================================================================
 *  Enable MSGQ and POOL Managers
 *  ===========================================================================
 */
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;

/*  ===========================================================================
 *  Set all code and data sections to use DDR
 *  ===========================================================================
 */
bios.setMemCodeSections (prog, bios.DDR2) ;
bios.setMemDataNoHeapSections (prog, bios.DDR2) ;
bios.setMemDataHeapSections (prog, bios.DDRALGHEAP) ;

/*  ===========================================================================
 *  MEM : Global
 *  ===========================================================================
 */
prog.module("MEM").BIOSOBJSEG = bios.DDRALGHEAP;
prog.module("MEM").MALLOCSEG  = bios.DDRALGHEAP;

/*  ===========================================================================
 *  TSK : Global
 *  ===========================================================================
 */
prog.module("TSK").STACKSEG = bios.DDRALGHEAP ;

bios.TSK.instance("TSK_idle").stackSize = 0x1000;

//Fix for clock
prog.module("CLK").SPECIFYRATE = true;
prog.module("CLK").INPUTCLK = 148.5;

/*  ===========================================================================
 *  Generate configuration files...
 *  ===========================================================================
 */
if (config.hasReportedError == false) {

bios.MEM.instance("IRAM").createHeap = 1;
bios.MEM.instance("IRAM").heapSize = 0x10000;
bios.MEM.instance("IRAM").enableHeapLabel = 1;
bios.MEM.instance("IRAM").heapLabel = prog.extern("IRAM_HEAP", "asm");
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!

    prog.gen();
}