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Hi Lars

PinMux and Module clock configuration support for McSPI Instance 1 was not provided because on EVMAM335x McSPI Instance 0 was connected to SPI-Flash.

To enable pin mux and clock to McSPI Instance 1 these are the changes to be done -

 Replace these lines of code(in the platform file)-

      /* PinMux for SPI1 CLK */

1)  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) =  (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                                                                                                                                        CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);

     with

     HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = 0x32;

     /* PinMux for SPI1 D0*/

2) HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) =  (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                                                                                                                                  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);

      with

      HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) = 0x32;

     /* PinMux for SPI1 D1 */

3) HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) =  (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                                                                                                                                  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE); 

      with

     HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) = 0x32;

4) HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS0) = (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                                                                                                                                    CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);

     with

     HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) = 0x32;

     0x32 stands for MUXMODE - 2, PullUp/PullDwn Enabled, PullUP Selected, Rx Enabled

5) In McSPI0ModuleClkConfig function replace the below lines of code

    HWREG(SOC_CM_PER_REGS + CM_PER_SPI0_CLKCTRL) &= ~CM_PER_SPI0_CLKCTRL_MODULEMODE;

    HWREG(SOC_CM_PER_REGS + CM_PER_SPI0_CLKCTRL) |= CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE;

   while((HWREG(SOC_CM_PER_REGS + CM_PER_SPI0_CLKCTRL) & CM_PER_SPI0_CLKCTRL_MODULEMODE) !=    CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE);

with

HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &= ~CM_PER_SPI1_CLKCTRL_MODULEMODE;

HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) |= CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &
      CM_PER_SPI1_CLKCTRL_MODULEMODE) != CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE);

Also in the McSPI application file replace the macro SOC_SPI_0_REGS with SOC_SPI_1_REGS.

Regards

Jeethan

Hi Jeethan,

Thank you for your reply. Unfortunately it seems that altering the code as you suggested did not result in the interface working. I started looking into what your commands did. Looking at my beaglebone schematics I can see that MCASP0 ACLKX lies on the same pin as SPI1 CLK, so I tried swapping your CONTROL_CONF_MII1_COL with CONTROL_CONF_MCASP0_ACLKX, and the rest of them accordingly. This at least caused the pins to go from low to high when their respective commands were executed according to my logic analyzer.

However, it still seems that the actual transmission will not go through, the pins stay high after their muxing... I'm attaching my files. If you have any possibility to shine some more light on the problem that would be greatly appreciated! Do note that I have not changed function names accordingly, they still claim it's SPI0 even though I modified their contents to SPI1.

0081.BONE_SCH.pdf

7140.SPI.zip

Kind regards

Lars

Lars

Great news :)

Anytime for help :)

Regards

Jeethan

      I am really glade that I found your message about getting SPI1 functional. I am designing a Cape card for the BeagleBone and need to control it from SPI1. I had struggled for several hours/days to get it working. Most of the problem was with StarterWare itself. Those imbedded Libraries should not be allowed and since each project has its own, makes it even more confusing.  Anyway, I have my SPI1 now functional thanks to your inputs and messages.

Best regards

Larry

Good to hear I'm not the only one who had troubles getting it to work, I'm glad my posts could be of assistance Larry :)

Kind regards

Lars

  I did have one other problem, The MOSI & MISO default were backwards. I added the command McSPIDataPinDirectionConfig to reverse them. When i looked at schematic, I saw SP1_D0 and SPI_D1. i assumed that that was a DO & DI, its not.  Its really is D0(zero)  &D1(one).  I then found in the AM335 data sheet that they can be made as an input or output and there is a command to reverse them.

Best Regards

Larry

Hi Jeethan,

I have a question that is related:

Why are all the pins set up with the RXACTIVE field set as "1 = receiver enabled"?

The SPI clock pin, chip select pin and MOSI pin are outputs so I'd expect these to have the RXACTIVE field set as "0 = receiver disabled".  I've tried using this set up and it didn't work, I'd just like to understand why.

Thanks,

Rog

Hi Roger,

As per my understanding the internal SPI clock is sourced through the output buffer to the AM335x IO pad and looped back into the device through the input buffer.  This is done so the internal SPI logic operates with a clock that has similar timing as the SPI device. Otherwise the AM335x output buffer delay would cause the internal SPI clock to appear several ns early relative to the other SPI signals.

Regards,

Jeethan