For those of us using cache, I think the IRQHandler and FIQHandler should replace the DMB instruction with the DSB instruction. DMB is a subset of DSB.
Note
mcr p15 0, r0, c7, c10, 4 ;;same as DMB (Data Memory Barrier)
mcr p15, 0, r0, c7, c10, 4 ;; same as DSB (Data Synchronisation Barrier)
Anyway, I am not 100% sure about this but ARM has at least one 28 page document I found about DSB, DMB, ISB.
Hi Brad,
Which versoin of StarterWare you are referring to ? Could you please check StarterWare_02_00_00_06 exceptionHandler.S ? I could not see any operation you mentioned above. Only DSB instruction is present in IRQ Handler.
Regards,
Sujith.
This is from AM335X_StarterWare_02_00_00_06\examples\evmAM335x\isr_reloc\exceptionhandler_gcc.S and it uses DMB. You will also see it in exceptionhandler_ewarm.S and exceptionhandler_cgttms470.asm. You will also see it in FIQHandler in those files. I sometimes look at things in multiple versions of assembler since I use RVDS4.1 which has a slightly different syntax than anything in StarterWare.
@*****************************************************************************
@* Function Definition of IRQ Handler@******************************************************************************
@
@ The IRQ handler jumps to the ISR of highest priority pending IRQ.
@ This handler doesnot support nesting.
IRQHandler:
STMFD r13!, {r0-r3, r12, r14} @ Save context in IRQ stack
LDR r0, =ADDR_SIR_IRQ @ Get the Active IRQ
LDR r1, [r0]
AND r1, r1, #MASK_ACTIVE_IRQ @ Mask the Active IRQ number
LDR r0, =fnRAMVectors @ Load the base of the vector table
ADD r14, pc, #0 @ Save return address in LR
LDR pc, [r0, r1, lsl #2] @ Jump to the ISR
MOV r0, #NEWIRQAGR @ Acknowledge the current IRQ
LDR r1, =ADDR_CONTROL
STR r0, [r1]
DMB @ Barrier to complete the data write
LDMFD r13!, {r0-r3, r12, r14} @ Restore registers from IRQ stack
SUBS pc, r14, #0x4 @ Return to program before IRQ
This was for the ISR relocation example. I suggest to use the exception handler at /system_config/armv7a/am335x/<toolchain>/