Hi all.
I'm testing the uartEcho example from the StarterWare 02.00.00.05 on the AM3358 evaluation kit.
It works.
When I change the uart FIFO TRANSMITTER trigger level (txTrigLvl) with a value like 3, the uart Tx Fifo doesn't wait 3 characters to send data but sends each byte immediatly.
I tried to call UARTFIFOEnable(baseAdd) without success.
Any suggestions ?
Hello Mickael,
Firstly, I would like to briefly explain the structure of the UART Interrupt application (uartEcho), though the flow is quite obvious.
The idea that I am trying to stress here is that if interrupts are enabled, the data is written/read from the FIFO in the ISR. This is usually followed as a standard practice.
Transmit Trigger Level
Secondly, I would like to briefly explain the meaning of Transmit Trigger Level.
The Transmit Interrupt is raised when the number of bytes in the Transmit FIFO is less than the Transmit Trigger Level. Once sufficient numbers of bytes are written to the Transmit FIFO so that the number of bytes crosses the Transmit Trigger Level, the Transmit interrupt is de-asserted. It is again asserted if the number of bytes falls short of the Transmit Trigger Level. The following figure explains it well.
UARTCharGet() transmits single bytes
True. The above function transmits single bytes. This is used in the ISR because the Transmit trigger level used is 1. If multiple bytes are required to be transmitted, then use the utility function UARTPuts().
This function can be found in ‘utils/uartStdio.c’.
I have rewritten the ISR using UARTPuts() which I think would help you.
static void UARTIsr(void)
{
static unsigned int txStrLength = sizeof(txArray);
static unsigned int count = 0;
unsigned char rxByte = 0;
unsigned int intId = 0;
/* Checking ths source of UART interrupt. */
intId = UARTIntIdentityGet(SOC_UART_0_REGS);
switch(intId)
{
case UART_INTID_TX_THRES_REACH:
if(txStrLength > 0)
{
/* Transmitter FIFO length is 64 bytes. */
if(txStrLength < 64)
{
UARTPuts(txArray + count, txStrLength);
txStrLength = 0;
}
else if(txStrLength >= 64)
{
UARTPuts(txArray + count, 64);
count += 64;
txStrLength -= 64;
}
}
else
{
/* Disabling the THR interrupt. */
UARTIntDisable(SOC_UART_0_REGS, UART_INT_THR);
}
break;
……………………………..
………………………………
………………………………
}
By writing 64 bytes to the TX FIFO at one shot, we are actually buying good amount of time for the processor to do other tasks before we get another Transmit Interrupt. The next transmit interrupt is generated when the UART transmits bytes and the byte count drops below the trigger level.
Thus, irrespective of the Transmit Trigger Level, the TX FIFO could be filled to the brim if there are sufficient numbers of bytes to be transmitted.
Please revert back if you have any queries.
Thanks and Regards.
Gurudutt.
