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Am3352 CPSW software application problem

Other Parts Discussed in Thread: AM3352

Hi ,

 I meet some difficuties during the Rece/trans ethernet frames, detail as follows,

Background:CCS  +  AM335X_StarterWare_02_00_01_01 mornitor SW:Wireshark

Phenomenon:

 The ethernet frame received and send is not stable,the tx frame not transmit sometime when Tx hdr has  written successfully,the fail rate is about one fifth.

Detail:

   Some change made in cpswif_rx_inthandler,it just save the Rx frame to my buffer,and i will handle them in the main loop. 

and write the send ETH frame API:

signed char  CPSW_Send( struct netif *netif, unsigned char*buf,unsigned int len)

{  

struct pbuf *p;   

 p = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
  if (!p || 1!=p->ref)
  {
   ConsoleUtilsPrintf("pbuf_alloc failed!\n", -1);
   while (1) ;
  }
memcpy(p->payload,buf,len);

delay(5);  

cpswif_output(netif,p);

pbuf_free(p);  

return 0;

}

And some print message added as follows,

A: in cpswif_rx_inthandler

comment out  the handle session

/*if(ethernet_input((struct pbuf *)pbuf, netif_arr + if_num) != ERR_OK)                                                                         { Adjust the link statistics LINK_STATS_INC(link.memerr);

LINK_STATS_INC(link.drop); }*/  

add

1. ConsoleUtilsPrintf("copy rx to 0x%08x --", &(ETHRxFrameBuffer[ETHRX_IN_index].buffer)); //copy frame to my buufer

2. ConsoleUtilsPrintf("RxISR CP at 0x%08x --", curr_bd); 

 // Acknowledge that this packet is processed 

CPSWCPDMARxCPWrite(cpswinst->cpdma_base, 0, (unsigned int)curr_bd);

B: in cpswif_tx_inthandler :

add   

ConsoleUtilsPrintf("TxISR CP at 0x%08x---", curr_bd);//add   

/* Acknowledge CPSW and free the corresponding pbuf */   

CPSWCPDMATxCPWrite(cpswinst->cpdma_base, 0, (u32_t)curr_bd);

 

C:in cpswif_transmit

   if(curr_bd->flags_pktlen & CPDMA_BUF_DESC_EOQ)     {      

ConsoleUtilsPrintf("TxHdr at 0x%08x sending---\n",bd_to_send);//add      

/* Write the Header Descriptor Pointer and start DMA */      

CPSWCPDMATxHdrDescPtrWrite(cpswinst->cpdma_base,(u32_t)(bd_to_send), 0);

}

Test step:

using PC SW send  UDP frame, and Am335x should return according UDP frame.Once PC received successfully,delay about 4 seconds and send  again, and again,  till up to 30 times then stop,  the printf message as follows,(PC IP:192.168.1.100; AM3352 IP:192.168.1.3)

------------------------------------------------------------------

copy rx to 0x8009fd5c --RxISR CP at 0x4a103244 --process bd at 0x8009fd5c --TxHdr at 0x4a102280 sending--- TxISR CP at 0x4a102280---process Rx times is 1---

copy rx to 0x800a0350 --RxISR CP at 0x4a103258 --process bd at 0x800a0350 --TxHdr at 0x4a102294 sending--- TxISR CP at 0x4a102294---process Rx times is 2---

copy rx to 0x800a0944 --RxISR CP at 0x4a10326c --process bd at 0x800a0944 --TxHdr at 0x4a1022a8 sending--- TxISR CP at 0x4a1022a8---process Rx times is 3---

copy rx to 0x800a0f38 --RxISR CP at 0x4a103280 --process bd at 0x800a0f38 --TxHdr at 0x4a1022bc sending--- TxISR CP at 0x4a1022bc---process Rx times is 4---

copy rx to 0x800a152c --RxISR CP at 0x4a103294 --process bd at 0x800a152c --TxHdr at 0x4a1022d0 sending--- TxISR CP at 0x4a1022d0---process Rx times is 5---

copy rx to 0x800a1b20 --RxISR CP at 0x4a1032a8 --process bd at 0x800a1b20 --TxHdr at 0x4a1022e4 sending--- TxISR CP at 0x4a1022e4---process Rx times is 6---

copy rx to 0x800a2114 --RxISR CP at 0x4a1032bc --process bd at 0x800a2114 --TxHdr at 0x4a1022f8 sending--- TxISR CP at 0x4a1022f8---process Rx times is 7---

copy rx to 0x800a2708 --RxISR CP at 0x4a1032d0 --process bd at 0x800a2708 --TxHdr at 0x4a10230c sending--- TxISR CP at 0x4a10230c---process Rx times is 8---

--------------------------------------------------------------

It is strangely that the PC stop sending cause it did not received the echo frame after print"process Rx times is 8" ,at the same time  the wireshark just has 15 frames(just be lack of the last echo).

The question is that the TxHdr has write and jump into the Tx_ISR, and print  "TxISR CP at 0x4a10230c",why no data send out? And this time if i send UDP to Am335x manually,it CAN feedbake successfully sometimes.

Till now,i have learned sth from the driver in cpswif.c. During the init, enable the ISR No. 41/42 in AintcCPSWIntrSetUp, and enable the interrupts for channel 0 and for control core 0 . What is the relationship between them?

My understanding is when write the TxHdr ,it should start DMA ,and then fire the Tx ISR ,jump into cpswif_tx_inthandler ,then send data out. If I am wrong, please correct it directly,thanks.

And what about Rx process?

Are there  some other detail should be printed out or something I missed?     

Could someone kindly  give me some advice? Thanks for ahead.

 

Regards,

stone