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Eth Phy Stops Working in AM335x EVM Starter KIt

Dear Team,

                       We are working on a project which requires RGMII operation for better performance. So we choose EVMSK for development purpose and try to enable the Internal Delay mode of RGMII Ethernet PHY (AR 8031).The errata of EVM SK says, for RGMII operation enable the Internal Delay mode by software using PHY Registers.

We are using

CCS Version : 5.3 and

SDK: Starterware 02.00.01.01.

As per our Understanding we follow the below Steps to enable the Transmitter Clock internal Delay mode, After doing Changes the PHY stops Working.

1.The Receiver Clock Internal Delay mode is Enabled by default(After H/W and S/W reset),So We just Read the value for Verification of Our Code.

2.The Transmitter Clock Delay mode is disable by default(After H/W and S/W reset),So first We read the Value of offset Register(0X05) by writing Register index(0x05) into the Debug1 Register of PHY and Read the value from the Debug 2 Register of PHY.

3.The value obtained is 0X2C47(value Should be 0X0000 according to data sheet).

4. We Set the Appropriate bit in the value(8th Bit value is 0X2D47) obtained and write into the register(Debug2).

5.After Writing, Perform Read operation to know the value is Correctly Written or Not.

6.Value Obtained is 0X2D47.

This is the piece of code  added into the PHY Driver file  and cpswif porting file.

Macros used for R/W Eth Phy registers

#define PHY_DEBUG1             0X1D  /* Offset Address of PHY DEBUG 1 Register */
#define PHY_DEBUG2             0X1E  /* Offset Address of PHY DEBUG 2 Register */

#define REG_OFFSET_RX     0X0000   /* Offset Address to Enable Rx clock internal Delay mode */
#define REG_OFFSET_TX     0X0005   /* Offset Address to Enable Tx Clock Internal; Delay mode */

#define DELAY_VAL_RX      0X8000     /* Value to enable the rx clock internal Delay mode */
#define DELAY_VAL_TX      0X0010     /*  Value to enable the Tx Clock Delay mode */

#define RX_MODE   0X1
#define TX_MODE   0X2  

Phy.c file

unsigned int PhyInternalDelayRead(unsigned int mdioBaseAddr, unsigned int phyAddr,
                              unsigned char mode, unsigned short *val)
{

    if(mode == RX_MODE) {
        
        MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_DEBUG1, REG_OFFSET_RX );
    
    }
    else if(mode == TX_MODE) {
        
        MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_DEBUG1, REG_OFFSET_TX );

    }
    
    if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_DEBUG2, val) != TRUE )
    {
        return FALSE;
    }
   
    return TRUE;

}

void PhyInternalDelayWrite(unsigned int mdioBaseAddr, unsigned int phyAddr,
                              unsigned char mode, unsigned short *val)
{


    if(mode == RX_MODE) {
        
        MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_DEBUG1, REG_OFFSET_RX );
    
    }
    else if(mode == TX_MODE) {
        
        MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_DEBUG1, REG_OFFSET_TX );

    }
    
    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_DEBUG2, *val );
    
}

cpswif Porting file:

 unsigned short val = 0;
  if( PhyInternalDelayRead(cpswinst->mdio_base, cpswinst->port[slv_port_num -1].phy_addr,
                        TX_MODE, &val) == TRUE  ) {
      LWIP_PRINTF("\n\rInternal Delay Read Successful:tx."); 

   /*Value Obtained is 0X2C47 but According to Data Sheet of PHY it should be 0X0000 */
          if ( ( val >> 8 ) & 0x1 ) LWIP_PRINTF("\n\rInternal Delay is set:tx, val = 0x%x", val);
          else {
            LWIP_PRINTF("\n\rInternal Delay is not set:tx, val = 0x%x", val );
            val = ( val | 0x0100 );
            PhyInternalDelayWrite(cpswinst->mdio_base, cpswinst->port[slv_port_num -1].phy_addr,
                        TX_MODE, &val);
        }  
    }    
 else {
    LWIP_PRINTF("\n\rInternal Delay Read Not Successful.:tx");
  }
   val = 0X0000;
  if(PhyInternalDelayRead(cpswinst->mdio_base, cpswinst->port[slv_port_num -1].phy_addr,
                        TX_MODE, &val) == TRUE ) {
      LWIP_PRINTF("\n\rInternal Delay  Read Successful:tx.");

            if((val >> 8) & 0x1 ) LWIP_PRINTF("\n\rInternal Delay is set:tx, val = 0x%x", val);
      }    
 else {
    LWIP_PRINTF("\n\rInternal Delay Read Not Successful:tx.");
  }
  val = 0x0000;     
  if(PhyInternalDelayRead(cpswinst->mdio_base, cpswinst->port[slv_port_num -1].phy_addr,
                        RX_MODE, &val) == TRUE ) {
     LWIP_PRINTF("\n\rInternal Delay Read Successful:rx.");

   /* Value Obtained is 0X82EE and According to the Data Sheet of the PHY, Value After H/W or S/W Reset is 0x82EE  Internal Delay Mode is Enabled by default for Rx clock*/

    if( (val >> 15)  & 0X1) LWIP_PRINTF("\n\rInternal Delay is set:rx, val = 0x%X ", val);
     else LWIP_PRINTF("\n\rInternal Delay is not set:rx.");
  }
 else {
    LWIP_PRINTF("\n\rInternal Delay Read Not Successful.Rx");
 }

Any Suggestions greatly helpful.

Thanks & Regards

Rama Krishna