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am335x mcspi master mode question

Using ccs ,i just use spi0 only and  init two pins in sip0(CLK and DAT1 for receive),and enable the rx full ISR,when i write 16 bit data to Tx reg,oscilloscope the CLK output and received data in DAT1,but use the CCS to monitor the Rx reg value,it is the same as date write in Tx reg for the first time. and  when Rx_full set ,the code doest't jump into the ISR,is there something i missed? the modified place was colour bule and coda as follows,

SPI0Pinmux()

{

//SPI0_CLK : A17  

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = 0x30;

 //SPI0_D1:  B16  

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) =   0x30;

}

static void SPI0AintcConfigure(void)

{    

 /* Register McSPIIsr interrupt handler */    

IntRegister(SYS_INT_SPI0INT, McSPIIsr);

    /* Set Interrupt Priority */    

IntPrioritySet(SYS_INT_SPI0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enable system interrupt in AINTC */    

IntSystemEnable(SYS_INT_SPI0INT);

}

static void McSPISetUp(void)

{     /* Reset the McSPI instance.*/    

McSPIReset(SOC_SPI_0_REGS);//P4032

    /* Enable chip select pin.*/    

//McSPICSEnable(SOC_SPI_0_REGS);//mcspi_MODULCTR bit1 PIN34=0 //P4044    

McSPICSDisable(SOC_SPI_0_REGS);//cs not used

    /* Enable master mode of operation.*/    

McSPIMasterModeEnable(SOC_SPI_0_REGS);

    /* Perform the necessary configuration for master mode.*/

McSPIMasterModeConfig(SOC_SPI_0_REGS, MCSPI_SINGLE_CH, MCSPI_TX_RX_MODE,         MCSPI_DATA_LINE_COMM_MODE_5,  0);

    /* Configure the McSPI bus clock depending on clock mode. */     McSPIClkConfig(SOC_SPI_0_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ, 0, MCSPI_CLK_MODE_2);

    /* Configure the word length.*/    

McSPIWordLengthSet(SOC_SPI_0_REGS, MCSPI_WORD_LENGTH(16), 0);

    /* Set polarity of SPIEN to low.*/    

McSPICSPolarityConfig(SOC_SPI_0_REGS, MCSPI_CS_POL_LOW, 0);

    /* Enable the transmitter FIFO of McSPI peripheral.*/    

McSPITxFIFOConfig(SOC_SPI_0_REGS, MCSPI_TX_FIFO_ENABLE, 0);

    /* Enable the receiver FIFO of McSPI peripheral.*/   

McSPIRxFIFOConfig(SOC_SPI_0_REGS, MCSPI_RX_FIFO_ENABLE, 0);

 

//add    

HWREG(SOC_SPI_0_REGS + 0x17C) |= 0x101;// when Rx has two byte,then occur Rx ISR

      // SPIEN line is forced to low state.  

McSPICSAssert(SOC_SPI_0_REGS, 0);//p4046 bit20

McSPIIntEnable(SOC_SPI_0_REGS, MCSPI_INT_RX0_OVERFLOW | MCSPI_INT_RX_FULL(0));//P4040

 McSPIChannelEnable(SOC_SPI_0_REGS, 0);//p4051 channel0 enable

}

void SPI0_Init(void)

{

McSPI0ClkConfig();

SPI0Pinmux();

SPI0AintcConfigure(); 

McSPISetUp();

}

int main(void)

{

 IntAINTCInit();   

IntMasterIRQEnable();

 SPI0_Init();  

     while(1)  

      {   

      McSPITransmitData(SOC_SPI_0_REGS,0x5555, 0);   

      McSPITransmitData(SOC_SPI_0_REGS,0xAAAA, 0);

      }

}

Debug steps:

set breakpoint at  send data 0x5555 and 0xAAAA.

1.send 0x5555, can see Tx and Rx reg is 0x5555,and Rxfull set

2.send 0xAAAA, just Tx reg value change to 0xAAAA, others no change at all. 

3.repeat step1&2 about 8 times, i think all data can send success cause the output clk is ok .   at the ninth time,the  RXFFF was set and no clk output again.

i wonder how to triger the Rx ISR  and why the Rx reg value =0x5555 at the first send ?

should anyone can give me some suggestion?

thanks for ahead!