AM335X ethernet tx blocking

Jimmy Liao

Hi,

I'm using AM335X with ethernet and develop on starterware 02_00_01_01
When I setup ethernet register it's work normally, both web server is work.

But after I keep refresh web browser shortly, the ethernet is stall.
Even ping is not reachable.

I find TX0_HDP register is block when ethernet stall, and
cpswif_tx_inthandler is into timeout procedure.

Dose any idea to defend tx blocking or solve when tx is blocking?

//==========================================================================

Hi, thanks for reply

Sorry, LWIP_CACHE_ENABLE is my test procedure, I have remove it and test/post again

First picture is capture when interrupt generator.

Second picture is capture when ethernet block then I suspend by tool

Have any idea to defend tx blocking or solve when tx is blocking?

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Moving this to the Starterware forum.

0 Matthijs van Duin over 9 years ago

Mastermind 8020 points

Where'd that "ifdef LWIP_CACHE_ENABLED" block of code from? It isn't in the original cpswif.c from starterware, and definitely doesn't belong there: by "failed to transmit, give it a chance once more" the comment means "hasn't completed transmission, just return for now and we'll eventually get an irq again". There's no failure nor retrying/retransmission going on as the comment seems to imply, and modifying the content of curr_bd is forbidden since it is still owned by CPDMA.

0 Matthijs van Duin over 9 years ago

Mastermind 8020 points

Huh, okay, the starterware interrupt handling code is however definitely also mistaken: performing CPSWCPDMATxHdrDescPtrWrite again is only appropriate if the EOQ flag was set on the last descriptor even though its 'next' was non-NULL (can happen due to race condition). Otherwise, finding a descriptor with the OWNER flag set just means you should issue an eoi and return. I also don't understand why it's testing the flag 65535 times before doing so.

0 Matthijs van Duin over 9 years ago in reply to Matthijs van Duin

Mastermind 8020 points

It's worth mentioning that performing CPSWCPDMATxHdrDescPtrWrite when CPDMA in fact isn't idle will trigger a DMA Error condition which causes CPDMA to shut down entirely and require complete reset.

0 Jimmy Liao over 9 years ago in reply to Matthijs van Duin

Prodigy 40 points

Hi,

Thanks for reply.

1.Dose have any register to make sure CPDMA is error that need to complete reset?
2.Dose have any example about CPDMA complete reset procedure?

0 Matthijs van Duin over 9 years ago in reply to Jimmy Liao

Mastermind 8020 points

Jimmy Liao said:
1.Dose have any register to make sure CPDMA is error that need to complete reset?

Yes, the CPDMA DMASTATUS register will indicate this. There is also an associated irq, the raw status of which is bit 1 of DMA_INTSTAT_RAW (if enabled it becomes one of sources of the "misc irq")