I am trying to get an external SPI Master write data to the A8 SPI and than subsequently transfer that from FIFO to internal memory using DMA. I can get the described scenario to work with A8 being the Master but not with the A8 being the slave. I am using AM335X_StarterWare_02_00_01_01. I don't get any SPI DMA events or interrupts, whereas this works when A8 is in master mode implying the SPI and DMA is setup correctly. I don't know what else the A8 SPI-DMA slave mode needs in order to get the events. I am calling the following routines to set up the DMA for SPI.
EDMA3Initialize()
RequestEDMA3Channels()
McSpiRxEdmaParamSet()
McSPIDMAEnable()
I am using channel 0 of the McSPI1 instance and setting it's associated paramset as follows:
static void McSpiRxEdmaParamSet(unsigned int tccNum, unsigned int DMAchNum,
unsigned SPIchannel,
volatile unsigned char *buffer,
unsigned short buffLength,
unsigned int destBidxFlag)
{
EDMA3CCPaRAMEntry paramSet;
unsigned char *p = (unsigned char *)¶mSet;
unsigned int index = 0;
/* Clean-up the contents of structure variable. */
for (index = 0; index < sizeof(paramSet); index++)
{
p[index] = 0;}
/* Fill the PaRAM Set with Receive specific information.*/
/* srcAddr holds address of SPI Rx FIFO.*/
// paramSet.srcAddr = (unsigned int) (MCSPI_RX0_REG);
paramSet.srcAddr = (unsigned int) (SpiCommunication::UI_SPI_HW_BASE_ADDRESS + (MCSPI_RX(SPIchannel)));
/* destAddr is address of memory location named buffer.*/
paramSet.destAddr = (unsigned int) buffer;
/* aCnt holds the number of bytes in an array.*/
paramSet.aCnt = 1;
/* bCnt holds the number of such arrays to be transferred.*/
paramSet.bCnt = buffLength;
/* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred.*/
paramSet.cCnt = 1;
/* The srcBidx should not be incremented since it is a h/w register.*/
paramSet.srcBIdx = 0;
if(TRUE == destBidxFlag)
{
/* The destBidx should be incremented for every byte.*/
paramSet.destBIdx = 1;
}
else
{
/* The destBidx should not be incremented.*/
paramSet.destBIdx = 0;
}
/* A sync Transfer Mode. */
/* srCIdx and destCIdx set to zero since ASYNC Mode is used.*/
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
/* Linking transfers in EDMA3 are not used.*/
paramSet.linkAddr = 0xFFFF;
paramSet.bCntReload = 0;
paramSet.opt = 0x00000000;
/* Set TCC field in OPT with the tccNum.*/
paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* Now write the PaRam Set to EDMA3.*/
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, DMAchNum, ¶mSet);
/* EDMA3 Transfer is Enabled.*/
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, DMAchNum, EDMA3_TRIG_MODE_EVENT);
}