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about am335x RGMII

user1880966
Prodigy 10 points

I'd like to ask a question:

I have a Starter Kit and a homemade development board of AM335x.It in the hardware part is the same.It runing in the RGMII 1000BT mode.

homemade development board:

When running in the WINCE or Linux,the AM335x can received from PHY(AR8031).But it is failed when I runing in the Starterware(enteLwip).No data has been received.In the CPSW_STATS(0x4A100_900) ,it is always zero.But it's possible to transmit.I can received from am335x on the computer.

Starter Kit:

When running in the Starterware(enteLwip),the value of CPSW_STATS(0x4A100_900) has been growing.And I can transmit and receive on the computer.

Test:

1.I read the register from AR8031.He two are the same.

2.I read the register of PinMux from am335x.He two are the same.

So I don't know what to do.

Starterware is 02_00_01_01.Does it have a bug? Can you help me?

  • 0
    TI__Intellectual 1480 points

    If same configuration work on Starter kit, as part has not changed, it does not look to be software issue. Check the hardware difference for any pointers.

    Regards,

    Ramesh D

  • 0
    Intellectual 850 points

    I have the same problem. I see RMII signals, but do not see interrupt CPSW.

    My physics KSZ8041 in RMII mode. I checked his connection schematics for technical documentation. I have connected via JTAG and checked trace the signal flow on lines TXD0, TXD1, TXEN, RXDO, RXD1, RXER, CRS to the processor. I run an example Startervare EnetLwip for EVMSK in dual MAC mode. First port work fine. Second port have a problem. Transmit packets are sent is good - I see them in Wireshark. Reception packages are not accepted. No interrupt CPSW hardware. RMII signals on lines when receiving packets visible is good. Packages are sent is good, hence clocking RMII to the side the processor correctly.

    My pin MUX code is shown below:

    /*Pin Mux for RMII2  */
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) = 3;  //RMII2_TXD0
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = 3;  //RMII2_TXD1
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = 3;  //RMII2_TXEN
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = 0x22; //RMII2_CRS
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = 0x23; //RMII2_RXD0
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) = 0x23; //RMII2_RXD1
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) = 0x23;   //RMII2_RXERR
        HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = (1
            | (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT)
            | (1 << CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT));   //RMII2_REFCLK

    I dont know where to find cause of the problem. Any suggestions

  • 0 in reply to Vladimir
    TI__Mastermind 30365 points
    Vladimir,
    Please avoid posting multiple threads with the same question. I will close this thread and continue the discussion at e2e.ti.com/.../386023

    Lali