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McASP Unexpected Frame Sync Error

Hi Ti-Employee,

I have some problems with the McASP TX.
here are my settings:

Burst mode
8 Bit word
8 Bit slot
lsb first
internal framesync rising edge
MCASP_TX_SYNC_DELAY_1BIT
internal clk 3MHz falling edge
tx mode dma
EDMA PaRAM setting:
{
/*PaRAM entry set MCASP TX*/
(unsigned int) (0x02 << 8u) | ((EDMA3_MCASP_TX_CHA_NUM << EDMA3CC_OPT_TCC_SHIFT)
& EDMA3CC_OPT_TCC) | (1 << EDMA3CC_OPT_TCINTEN_SHIFT), // opt
(unsigned int) &txBuffer , // src
(unsigned short)1, // aCnt
(unsigned short)sizeof(txBuffer), // bCnt
(unsigned int) MCASP_DATA_REGS, // dest
(short) 1, // srcBIdx
(short)0x00, // destBIdx
(unsigned short)0xFFFF, // link
(unsigned short)0x00, // bCntReload
(short)0x00, // srcCIdx
(short)0, // destCIdx
(unsigned short)1 // cCnt
},

Evaluation Board is Beaglebone Black.

I want to transmit the txBuffer every 10 ms.
Of course the McASP is initialized and the serializer is enabled and so on.
Therefore every 10 ms I write the PaRAM entry to the McASP channel number and enable the EDMA transfer.

In EDMA complete ISR I disable the EDMA transfer.


The tx buffer will transmit one time, no more. I get in the McASP status register the errorCode:
XSTAT 0x00000122
When I use link-to-self Transfer it works but there is one sync too much and I have the same
XSTAT error.

I have also a missed event in the EDMA EMR register (channel 8).


I read in the Technical Reference Manual (SPRUH73L 22.2.10.4.1) some reason for exactly my problem (I think so)
but there are no approaches to solve such problems.

Unfortunately it is very important for our R&D to use McASP in this Burst Mode setup.

So what can I do ??
Hopefully you can help me with some hints and tricks to solve this problems.


Thanks for your help
Best Regards
Igi