ICE V2 BOOTING THROUGH NOR FLASH

Hi,

I will ask the Starterware team to help on this.

Thanks Biser,

I was hoping some help from you in this. Waiting for the reply as we would then look forward to buying ICE_V2.

Regards..

Hi Biser,

Is this something very complicated that may require lot of time? If the starterware community can update...

Hi Vinesh,

Thanks. Sorry for the mis-information. I have SDK1.1.0.8 only which is latest.

To further get into this NOR Flash Boot, I was going through boot_NOR_ICE_V2.cmd file which has the following description:-

/****************************************************************************/
-stack 0x0040 /* SOFTWARE STACK SIZE */
-heap 0x2000 /* HEAP AREA SIZE */
-e Entry
/* Since we used 'Entry' as the entry-point symbol the compiler issues a */
/* warning (#10063-D: entry-point symbol other than "_c_int00" specified: */
/* "Entry"). The CCS Version (5.1.0.08000) stops building from command */
/* line when there is a warning. So this warning is suppressed with the */
/* below flag. */

--diag_suppress=10063

/* -l ../../../../../../../binary/armv7a/cgttms470_ccs/am335x/drivers/drivers.lib */
/* -l ../../../../../../../binary/armv7a/cgttms470_ccs/am335x/evmAM335x/platform/platform.lib */
/* -l ../../../../../../../binary/armv7a/cgttms470_ccs/utils/utils.lib */
/* -l ../../../../../../../binary/armv7a/cgttms470_ccs/mmcsdlib/libmmcsd.lib */

-l drivers.lib
-l platform.lib
-l utils.lib
-l libmmcsd.lib


/* SPECIFY THE SYSTEM MEMORY MAP */

MEMORY
{
NOR_MEM : org = 0x08000000 len = 0x10000 /* RAM */
IRAM_MEM : org = 0x402F0400 len = 0x1FBFF /* RAM */
}

/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */

SECTIONS
{
.init : {
bl_init.obj (.text)
} load > 0x08000000
.const : load > NOR_MEM /* GLOBAL CONSTANTS */
.cinit : load > NOR_MEM
.text : load > NOR_MEM /* CODE */
.ram_code: { bl_norexec.obj(.text)} load > NOR_MEM

.data : load > IRAM_MEM /* INITIALIZED GLOBAL AND STATIC VARIABLES. */
.bss : load > IRAM_MEM /* UNINITIALIZED OR ZERO INITIALIZED */
/* GLOBAL & STATIC VARIABLES. */
RUN_START(bss_start)
RUN_END(bss_end)

.stack : load > 0x4030FF00 /* SOFTWARE SYSTEM STACK */

}

Here does NOR_MEM : org = 0x08000000 len = 0x10000 /* RAM */ mean 65,535 bytes are allocated for CSN0 i.e. on board NOR FLash? Why so when the memory is 16MB?

Again why the system memory map does not talk about system memory mapped to DDR3 and why only NOR and Internal SRAM?

Can you also guide me as to how to go about to understand this remaining file? Like does it mean that after booting and during the execution of the application code global constants and the code will be loaded from NOR Memory and the initialized and uninitialized variables will be loaded from Internal SRAM? Do we need to fiddle with this file at all? And will this file be changed in case we boot from an OTP rather than NOR?

Hi,

We have understood the above mentioned file by following ARM Compiler guide.

Kindly reply the remaining doubts of the previous posts:-

Here does NOR_MEM : org = 0x08000000 len = 0x10000 /* RAM */ mean 65,535 bytes are allocated for CSN0 i.e. on board NOR FLash? Why so when the memory is 16MB?

Again why the system memory map does not talk about system memory mapped to DDR3 i.e. 0x80000000 and why only NOR and Internal SRAM?

And will this file be changed in case we boot from an OTP rather than NOR?

But Walzer do you mean, we cannot use DDR in NOR boot configuration? I hope this not what you are saying.

Thanks Vinesh, I would continue this post for some more related query

Hi Vinesh and Walzer,

In my case my system will be boot with an OTP [XIP device on CSn0, 16 bit device - 1Mbit size] and will compute the check sum of the content of a parallel NOR Flash [on CSn1, 16 bit device - 1Gbit size]. Once the the checksum of the NOR Flash is found to be correct, the actual application will reside on the NOR flash and should be executed from there. While executing the boot code from OTP, DDR may not be used. But while using application code of NOR flash, DDR will be used.

Now how do the .cmd file change in that case as first the check sum routine within OTP will get executed and then application code within NOR flash will get executed and both will have .cinit, .const, .text etc.

We have never done such thing and so I am confused with this.

Please help.

I wait for our reply patiently...

If I am not understood kindly let me know, I can again explain my case

I mean how will that sequencing be done in .cmd file, if you could give some idea?

Thanks for the reply... It would be great if you could help me in this...

Kindly suggest other ways as well. I have understood what you are saying that develop two applications as per requirement and then sequence the two applications having their individual linker files. The sequencing can be through a SW reset and a flag that will not be reset even though SW reset has occurred.

But here there is a catch, once you say booting twice, then My both the devices are XIP devices and booting through XIP means through device on CSn0. My OTP will be connected on CSn0 and the NOR Flash be connected on CSn1. Can I do booting twice? Am I confused somewhere?

When you say:-

Then the boot laoder has to find the flag and now boot app2 instead of app1. But of course there are other ways to do this...

This means after reset again the boot loader runs on XIP but it will never run on CSn1.

Please reply as you find time..

Hi Walzer,

we wait for your valuable revert on this. Please find time...

Regards.