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AM43xx DDR3 initialization

Other Parts Discussed in Thread: SYSBIOS

I'm going through Starterware DDR3 initialization code and stumbled on the following line (6 similar lines):

HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);

EMIF_IODFT_TLGC is defined as 0x60, this is an offset into EMIF registers, TRM has full name IMIF4D_IODFT_TEST_LOGIC_GLOBAL_CTRL for it. However, the base offset in SOC_CONTROL_MODULE_REG is 0X44e10000 which is the base address for CONTROL_MODULE and offset 0x60 in CONTROL_MODULE is reserved. Same code is present in am43xx sysbios ind sdk 2.0.0.2 and sysbios ind sdk 2.1.0.1. Any other register accesses in same subroutine use correct base offset of EMIF address space:

/* Configure DDR I/O and Control module registers complete. */
HW_WR_REG32((SOC_EMIF_ADDRSP0_REG + EMIF_SDRAM_REF_CTRL), 0x80003000U);

The code works, i don't know why. DDR3 is initialized and data does not seem to disappear.

Is this mismatch of base address and register offset in this code correct? Should the first line be updated to use SOC_EMIF_ADDRSP0_REG? If no, why is it contradicting the TRM? If yes, why does this code appear to be working?

  • I changed to use SOC_EMIF_ADDRSP0_REG instead of SOC_CONTROL_MODULE_REG, no visible changes in behavior.
    Also, the values that are written into EMIF_IODFT_TLGC are:
    HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);
    HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002411U);
    HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);

    The first and last values are the EMIF_IODFT_TLGC register value at CPU reset, the second value in between has DDR PHY reset bit set, so this sequence (used twice) resets the PHY. If these writes go into the bit bucket, the DDR PHY won't get reset but it still seems to work fine.
  • This is a mistake in Starterware, the code is correct in AM437x GEL files.

    In AM437x_MMRs.gel the EMIF_IODFT_TLGC is defined as:

    #define EMIF_IODFT_TLGC                 (EMIF_BASE_ADDR + 0x0060)

    The write sequence in AM43xx_EMIFconfig_HWlvl.gel is:

        WR_MEM_32(EMIF_IODFT_TLGC             ,0x00002011);
        WR_MEM_32(EMIF_IODFT_TLGC             ,0x00002411);
        WR_MEM_32(EMIF_IODFT_TLGC             ,0x00002011);

    This is why I hate #define's, you can add two random numbers together and compiler will; never tell you that you're adding apples to oranges (SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC)...