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AM437x Bootloader

Other Parts Discussed in Thread: SYSBIOS

Hi,

We are using AM437x IDK board.

On C:ti\sysbios_ind_sdk_2.1.0.1\sdk\starterware\bootloader\src\am43xx\sbl_am43xx_platform_pll.c file, it is mentioned as a comment that the DDR running frequency of GP EVM is 400 Mhz and IDK EVM is 333MHZ , But the register values for both are same. Can you Please clarify this Comment? The above mentioned section of code is as shown below.

if(BOARD_GPEVM == boardId) /* For GP EVM - 400 MHz */
{
ddrDpllDiv = 2U;
ddrDpllMult = 50U;
ddrDpllPostDivM2 = 1U;
ddrDpllPostDivM4 = 2U;
}
else if(BOARD_IDKEVM == boardId) /* For IDK EVM - 333 MHz */
{
ddrDpllDiv = 2U;
ddrDpllMult = 50U;
ddrDpllPostDivM2 = 1U;
ddrDpllPostDivM4 = 2U;
}

Also its is mentioned that the Values need to be checked as a TODO item. 

/* TODO: This valueis wrong need to check. Currently forced to 24MHz. */

if((BOARD_GPEVM == boardId) || (BOARD_IDKEVM == boardId)) /* For GP and IDK EVM 24MHz */
{
crystalFreqSel = 1U;
}

Can you please clarify the above mentioned comments in starterware\bootloader\src\am43xx\sbl_am43xx_platform_pll.c file?

 

Regards,

Jinu

  • Jinu,

    I looked at the GEL file from the latest CCS 6.1.1, under ccsv6\ccs_base\emulation\boards for GP and IDK 437x EVMs. The DDR PLL is set to both 400MHz with 2, 50, 1,2, this matches the code in the bootloader you mentioned:

            ddrDpllDiv = 2U;
            ddrDpllMult = 50U;
            ddrDpllPostDivM2 = 1U;
            ddrDpllPostDivM4 = 2U;

    So the comments /* For IDK EVM - 333 MHz */ is wrong.

    Regarding read in the clock frequency. Both Gel and bootloader code use the register 0x44e1_0040 bit 22-23 to determine the input clock, it is 24MHz. I am not sure of the history of bootloader code why they need to force the input clock based on the board type. I will need to check and post feedback here.

    Regards, Eric 

  • The usage in the latest CCS GEL file is correct, the bootloader code needs clean-up, I opened a ticket for this.

    Regards, Eric