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enable SPI channel 3 to 5 on AM4377

gopherfirm
Intellectual 270 points

Hello All,

Currently I have some testing with SPI interface using AM437x. Do you have any idea how to enable SPI channel 3 to 5 since the exampleproject(pdk_am437x_1_0_1) codes enable only SPI1 and SPI2.

Thanks.

Leo

  • 0
    TI__Guru**** 393215 points
    Moving this to the Starterware forum.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    Leo,

    Sorry for the late response. I investigated and found there is no issue for enabling SPI for all 5 instances. Here is the detail:

    SPI means MCSPI, not QSPI, for AM437x it has 5 instances.

    The investigation is based on Processor SDK 2.0.1 release, MCSPI_BasicExample_idkAM437x_armExampleProject using the SPI driver under pdk_am437x_1_0_1\packages\ti\drv\spi. There is:

    /* McSPI serializer instance */

    #define BOARD_MCSPI_SERIALIZER_INSTANCE 1=====> you can change from 0 to 4, corresponding 5 SPI instances.

    I also traced code, there are structures to hold the instances when SPI_open() is called.

    /* SPI configuration structure */
    const SPI_config_list SPI_config = {
        {
            &SPI_FxnTable_v1,
            &SpiObjects[0],
            &spiInitCfg[0]
        },
        {
            &SPI_FxnTable_v1,
            &SpiObjects[1],
            &spiInitCfg[1]
        },
        {
            &SPI_FxnTable_v1,
            &SpiObjects[2],
            &spiInitCfg[2]
        },
        {
            &SPI_FxnTable_v1,
            &SpiObjects[3],
            &spiInitCfg[3]
        },
        {
            &SPI_FxnTable_v1,
            &SpiObjects[4],
            &spiInitCfg[4]
        },
        {
            &QSPI_FxnTable_v1,
            &QspiObjects[0],
            &qspiInitCfg[0]
        },
        /* "pad to full predefined length of array" */
        {NULL, NULL, NULL}
    };

    In the real function SPI_open_v1() I set break point to watch "hwAttrs->baseAddr" to make sure the correct base address is passed when using instances 0 to 4.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 270 points
    Hello Eric,

    Thanks for your reply..

    Maybe there is no issue with spi enabling. I also tried the same thing but I would like to clarify something about spi registers which I dont know yet if my problem is related to spi enabling or not.

    This is the event:

    Upon checking MCSPIO0 or MCSPI1 I could see values under this registers but when I checked MCSPI2 to MCSPI4 the values are error: unable to read.

    sample Register Values:

    Name Value Description
    MCSPI0 to MCSPI1
    MCSPI_HL_REV 0x40300A0B IP Revision Identifier
    .......etc

    MCSPI2
    MCSPI_HL_REV Error: unable to read IP Revision Identifier
    ...... etc Error: unable to read



    With this case, does is mean that my spi channels are not yet correctly enable though I already changed the SPI instances to 4 which is the source of my question on how to enable all spi or do I need to configure other settings for this registers to have values like MCSPI0 and MCSPI1.

    If there is any, where can I found the source code to modify from PDK sample project related to initial spi register values?


    Thank you.

    Best regards,
    Leo
  • 0 in reply to gopherfirm
    TI__Guru* 95265 points

    Leo,

    Thanks for clarification! I saw that MCSPI 0 and 1 registers can be read out, however 2, 3 and 4 registers can't be read out as you said. The SPI_open_v1() aborted during McSPIReset() call. This needs further debug and I will create a ticket for this. The code for register programing is inside SPI_lld_v1.c.

    Regards, Eric 

  • 0 in reply to lding
    Intellectual 270 points

    Hello Eric,

    Any feedback about reading register of MCSPI 2 to MCSPI 5?

    I have tried to changed something inside SPI_lld_v1.c but still without success in enableing the initial register value.

    Thanks.

    Kind regards,

    Leo

  • 0 in reply to lding
    Intellectual 270 points

    Thanks Eric.

    Regards,

    Leo