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AM335X SPI with DMA - problems with FIFO

Hi,

I am using in my system SPI DMA code based on Starterware 02.00.01.01

I could not get it working - clock and CS were working properly ( checked on scope), but not data going out. Hardware was ok, as it worked with interrupt based SPI code.

After some testing I found out that if I *DISABLE* fifo (by clearing FFER/FFEW bits) , then DMA code works properly ( I can see data on the bus) . So few questions:

- Why FIFO operation does not work ? ( the line gets only zeros )  

- Why there is DMA 256 bit aligned mode - with special DAFTX/DAFRX registers ? What is the benefit ?

I also have not noticed any cache flush/invalidate code in the samples - but I guess once cache is enabled and DMA is being used then it should be used ?