I'm using a beaglebone black with StarterWare and need to enable the L1 and L2 cache for performance reasons. When I do so using CacheEnable(CACHE_ALL) and the MMU being configured as in the uartEdma_Cache.c example, performance goes down a lot.
I get a lot of interrupts from the DMA controller (McASP and Ethernet) so there are many unpredictable branches, which hurt the instruction cache, I guess (is factor 10 realistic?). I also tried using instruction cache only and using data cache only but I get about the same results. This even happens with L2 cache being disabled when only using L1 instruction cache what doesn't make any sense to me. How can loading single instructions from DDR be that much more efficient than the L1 instruction cache, even with all those cache misses?
Thats where I begin to doubt the assumption about the DMA interrupts being the source of the problem. Unfortunately the debugger doesn't help because you cannot inspect the cache. I ran out of ideas about what to test to find the source of the problem.
Has anybody seen similar problems using the cache on AM335x and found a way to fix it, or any ideas what I could try next?
Best Regards!
For reference: I asked this question in the Sitara Forum and was asked to ask in the StarterWare forum.