Hello everybody,
I’m quite a noobie and currently trying to understand and configure the pwm module of my beaglebone white (am335x sitara processor), using the starterware’s functions. As I see it, there are two ‘crucial’ regs, tbprd and tbclk.
Let me explain how I perceive the way things work, after reading the manual and please correct me if I'm mistaken. So, as I see it, the pwm module is clocked by the SYSCLKOUT , which in order to achieve a variety of produced pwm frequencies, we can use it in prescaled versions. The prescaled version is named TBCLK and it is given by the relation: TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV) as it is said in the manual (@section 15.2.4.1, TBCTL Register).
Since we have this value, and as I can see in starterware’s function EHRPWMPWMOpFreqSet(unsigned int baseAddr,unsigned int tbClk,unsigned int moduleClk), TBPRD can then be calculated as followed:
TBPRD=TBCLK/DESIRED_PWM_FREQUENCY : if up or down count, or
TBPRD=TBCLK/(2*DESIRED_PWM_FREQUENCY) : if up and down count
which is also justified in the manual. Therefore, with those the pwm frequency is fully determined.
Is the concept right or am I missing something?
Further questions:
1) how do we really choose what fragment of the module’s clock we need?
2) how do we choose the HSPCLKDIV and the CLKDIV bits? i.e if I want the product of those two to be 128 should I choose CLKDIV=128 and HSPCLKDIV=1 or let’s say CLKDIV=16 and HSPCLKDIV=8? What is the difference?
3) why is the TBPRD calculated as mentioned, in the up or down count? As I guess the formula is derived (at least it matches with the up and down count case) from those given in the manual (figure 15-12 @15.2.2.3.3 section) [which are: Tpwm=2*TBPRD*Ttbclk⇔Tpwm=2*TBPRD*(1/freq_TBCLK) and Tpwm=(TBPRD+1)*Ttbclk].
As a result, in the up or down count, shouldn’t it be something like TBPRD=(TBCLK/Tpwm)-1?
Thanks in advance, i hope i expressed myself clearly and sorry if I didn’t post it in the right place.