Tool/software: Starterware
Ti,
I am attempting to get two independent Ethernet interfaces up and running on an AM3358BZCZA100. The first interface is working OK but the second interface isn't receiving or transmitting. Taking receive as the example, I can see the receive ISR being called when broadcast packets arrive on port 1, but not on port 2.
The second interface is successfully negotiating an ethernet link to the switch and the MDIO_ALIVE & MDIO_LINK status bits in the CPSW are set, indicating the PHY is active (plus the link and activity lights are flashing). I can see those bits updating when I remove and insert the cable.
Looking at the AM3358 TRM I couldn't find a procedure for configuring the CPSW as two independant interfaces. Could you provide the correct sequence or failing that please take a look at the psuedo code below and indicate what I need to do to complete the correct configuration of the CPSW?
Both interfaces are plugged into a basic Netgear FS108 switch (no VLAN support) and configured with static IP addresses on independent subnets.
Interface 1: 192.168.20.32
Interface 2: 192.168.21.32
The AM3358 and first ethernet interface are running on an in-house PCB and the the second interface's PHY is a Micrel KSZ9031RNX PHY mounted on a second PCB (Micrel's eval kit) and connected to the first PCB by wires.
The software is based on SYS/BIOS and StarterWare (cpsw.c & mdio.c, etc) and the TCP/IP stack is LWIP. The cpswif.c file has CPSW_DUAL_MAC_MODE enabled.
Best regards,
Andrew.
The following initialization sequence was observed by stepping through the cpsw.c, mdio.c and cpswif.c files.
// CLOCK CONFIG
HWREG(SOC_CM_PER_REGS + CM_PER_CPGMAC0_CLKCTRL) =
CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE;
while(HWREG(SOC_CM_PER_REGS + CM_PER_CPGMAC0_CLKCTRL) !=
CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE);
while(0 != (HWREG(SOC_CM_PER_REGS + CM_PER_CPGMAC0_CLKCTRL) &
CM_PER_CPGMAC0_CLKCTRL_IDLEST));
HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0xFA
// CONFIGURE FIRST INSTANCE OF CPSW
cpswinst->ss_base = CPSW0_SS_REGS;
cpswinst->mdio_base = CPSW0_MDIO_REGS;
cpswinst->wrpr_base = CPSW0_WR_REGS;
cpswinst->cpdma_base = CPSW0_CPDMA_REGS;
cpswinst->ale_base = CPSW0_ALE_REGS;
cpswinst->cppi_ram_base = CPSW0_CPPI_RAM_REGS;
cpswinst->host_port_base = CPSW0_PORT_0_REGS;
cpswinst->port[PORT_1].port_base = CPSW0_PORT_1_REGS;
cpswinst->port[PORT_1].sliver_base = CPSW0_SLIVER_1_REGS;
cpswinst->port[PORT_1].phy_addr = CPSW0_PORT_1_PHY_ADDR;
cpswinst->port[PORT_1].phy_gbps = CPSW0_PORT_1_PHY_GIGABIT;
cpswinst->port[PORT_2].port_base = CPSW0_PORT_2_REGS;
cpswinst->port[PORT_2].sliver_base = CPSW0_SLIVER_2_REGS;
cpswinst->port[PORT_2].phy_addr = CPSW0_PORT_2_PHY_ADDR;
cpswinst->port[PORT_2].phy_gbps = CPSW0_PORT_2_PHY_GIGABIT;
CPSWSSReset(cpswinst->ss_base);
CPSWWrReset(cpswinst->wrpr_base);
CPSWSlReset(cpswinst->port[PORT_1].sliver_base);
CPSWSlReset(cpswinst->port[PORT_2].sliver_base);
CPSWCPDMAReset(cpswinst->cpdma_base);
MDIOInit(cpswinst->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);
delay(1);
// ALE PORT FORWARDING
CPSWALEInit(cpswinst->ale_base);
CPSWALEPortStateSet(cpswinst->ale_base, 0, CPSW_ALE_PORT_STATE_FWD);
CPSWALEPortStateSet(cpswinst->ale_base, 1, CPSW_ALE_PORT_STATE_FWD);
CPSWALEPortStateSet(cpswinst->ale_base, 2, CPSW_ALE_PORT_STATE_FWD);
// DUAL MAC MODE
CPSWALEVLANAwareSet(cpswinst->ale_base);
CPSWHostPortDualMacModeSet(cpswinst->host_port_base);
CPSWStatisticsEnable(cpswinst->ss_base);
// INITIALISE BUFFER DESCRIPTORS
cpswif_cpdma_init(cpswinst);
// TX AND RX RECEIVE INTERRUPTS
CPSWCPDMAEndOfIntVectorWrite(cpswinst->cpdma_base, CPSW_EOI_TX_PULSE);
CPSWCPDMAEndOfIntVectorWrite(cpswinst->cpdma_base, CPSW_EOI_RX_PULSE);
CPSWCPDMATxEnable(cpswinst->cpdma_base);
CPSWCPDMARxEnable(cpswinst->cpdma_base);
CPSWCPDMATxIntEnable(cpswinst->cpdma_base, 0);
CPSWWrCoreIntEnable(cpswinst->wrpr_base, 0, 0, CPSW_CORE_INT_TX_PULSE);
CPSWCPDMARxIntEnable(cpswinst->cpdma_base, 0);
CPSWWrCoreIntEnable(cpswinst->wrpr_base, 0, 0, CPSW_CORE_INT_RX_PULSE);
// INITIALIZE FIRST CPSW PORT
CPSWPortSrcAddrSet(cpswinst->port[0].port_base, (u8_t *)(&(cpswif->eth_addr)));
CPSWPortVLANConfig(cpswinst->port[0].port_base, curr_port, 0, 0);
cpswif_port_to_host_vlan_cfg(cpswinst, 0, (u8_t *)(&(cpswif->eth_addr)));
cpswif_phylink_config(cpswif, curr_port);
CPSWSlRGMIIEnable(cpswinst->port[0].sliver_base);
// INITIALIZE SECOND CPSW PORT
CPSWPortSrcAddrSet(cpswinst->port[1].port_base, (u8_t *)(&(cpswif->eth_addr)));
CPSWPortVLANConfig(cpswinst->port[1].port_base, curr_port, 0, 0);
cpswif_port_to_host_vlan_cfg(cpswinst, 1, (u8_t *)(&(cpswif->eth_addr)));
cpswif_phylink_config(cpswif, curr_port);
CPSWSlRGMIIEnable(cpswinst->port[1].sliver_base);
SetupHwi(SYS_INT_3PGSWRXINT0, CPSWCore0RxIsr, rx_isr_pri, 0);
SetupHwi(SYS_INT_3PGSWTXINT0, CPSWCore0TxIsr, tx_isr_pri, 0);