Starterware/AM3352: How to access GPMC addressing space for AM3352 to DSP TMS320VC5502

Tool/software: Starterware

HI All,

- Please check this code and guide, how CS configuration correct or not.

- My Task is to from provide a interface to AM3352 to GPMC and check signal in CRO, in CS pin of DSP.

- StarterWare_AM335X_02_00_01_01 

//----------------------------------------------------------------------------

// @INCLUDES
//-----------------------------------------------------------------------------

#include "hw_control_AM335x.h"
#include "consoleUtils.h"
#include "hw_cm_wkup.h"
#include "hw_cm_per.h"
#include "evmAM335x.h"
#include "soc_AM335x.h"
#include "interrupt.h"
#include "hw_gpmc.h"
#include "hw_types.h"
#include "gpmc.h"
#include "cache.h"
#include "mmu.h"
#include "delay.h"
#include "hw_types.h"
#include "gpio_v2.h"

#define GPIO_INSTANCE_PIN_NUMBER (27)

#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))

#define __raw_readl(a) (*(volatile unsigned int *)(a))

#define DSP_HPI_BASE 0x11000000 // CS = CS2

#define DSP_HPIC_LOW (DSP_HPI_BASE + 0x0000) // HPIC HIGH Byte
#define DSP_HPIC_HIGH (DSP_HPI_BASE + 0x0004) // HPIC LOW Byte
#define DSP_HPID_LOW (DSP_HPI_BASE + 0x0001) // HPID HIGH Byte (Auto Increment)
#define DSP_HPID_HIGH (DSP_HPI_BASE + 0x0005) // HPID LOW Byte (Auto Increment)
#define DSP_HPIA_LOW (DSP_HPI_BASE + 0x0002) // HPIA HIGH Byte
#define DSP_HPIA_HIGH (DSP_HPI_BASE + 0x0006)

//-----------------------------------------------------------------------------
// @FUNCTIONS
//-----------------------------------------------------------------------------

void GPMCPinMuxSetup(void);
void GPMCCSTimingConfigure();
void DspReset();

/**
*------------------------------------------------------------------------------
* @NAME : main
* @PARAM : NONE
* @PARAM : NONE
* @RETURNS : 0
* @BRIEF : main function of this application
*------------------------------------------------------------------------------
*/

int main(void)
{
unsigned int data = 0;
// unsigned int *ptr;

ConsoleUtilsPrintf("\n ************* AM3352 to GPMC interface Application ************\n");

// Enabling IRQ in CPSR of ARM processor
IntMasterIRQEnable();

// Initializing the ARM Interrupt Controller
IntAINTCInit();

// Configure a DMTimer instance
DelayTimerSetup();

// GPMC Pin mux setting
GPMCPinMuxSetup();

// GPMC Clock setting
GPMCClkConfig();

// GPMC Reset
GPMCModuleSoftReset (SOC_GPMC_0_REGS);

// Wait up to GPMC Reset status get
while ((GPMCModuleResetStatusGet(SOC_GPMC_0_REGS)) == 0);

// GPMC CS Configuration
GPMCCSTimingConfigure();

// DSP Reset
DspReset();


while(1)
{
ConsoleUtilsPrintf ("GPMC Mode selected to read\n");
data = __raw_readl(DSP_HPI_BASE);

ConsoleUtilsPrintf ("The data is:%x\n",data);
// data = 0;
delay(1000);

ConsoleUtilsPrintf ("GPMC Mode selected to Write\n");

__raw_writel(0x1234, DSP_HPI_BASE);

delay(1000);

ConsoleUtilsPrintf ("GPMC Mode selected to Read\n");

data = __raw_readl(DSP_HPI_BASE);

ConsoleUtilsPrintf ("The data is:%x\n",data);
// data = 0;
delay(1000);
}
ConsoleUtilsPrintf ("Program Executed Successfully\n");
} /* End of main */

void GPMCCSTimingConfigure()
{
// Disable the chip select2
GPMCCSConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_CS_DISABLE);

// CS2 Configuration timing
GPMCCSConfig1 (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x00001000);

// Configs the timing parameters for Chip Select signal
GPMCCSTimingConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x00101001);

// This function configs the timing parameters for ADV# signal
GPMCADVTimingConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x22060514);

// This function configs the timing parameters for WE# and OE# signal
GPMCWEAndOETimingConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x10057016);

// This function configs the RdAccessTime and CycleTime timing parameters
GPMCRdAccessAndCycleTimeTimingConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x010f1111);

// This function configs the Cycle2Cycle and BusTurnAround timing parameters
GPMCycle2CycleAndTurnArndTimeTimingConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x8f070000);

// Enables the chip select2
GPMCCSConfig (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_CS_ENABLE);

// set the base address for the chip select2
GPMCBaseAddrSet (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, 0x10);

//Set chip select mask address or size
GPMCMaskAddrSet (SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_CS_SIZE_16MB);

}

void DspReset()
{
GPIO1ModuleClkConfig ();

GPIO1Pin27PinMuxSetup ();

GPIOModuleEnable (SOC_GPIO_1_REGS);

GPIOModuleReset (SOC_GPIO_1_REGS);

GPIODirModeSet (SOC_GPIO_1_REGS, GPIO_INSTANCE_PIN_NUMBER, GPIO_DIR_OUTPUT);

GPIOPinWrite (SOC_GPIO_1_REGS, GPIO_INSTANCE_PIN_NUMBER, GPIO_PIN_LOW);
}

/**
*------------------------------------------------------------------------------
* @NAME : GPMCPinMuxSetup
* @PARAM : None
* @RETURNS : None
* @BRIEF : Initialize the GPMC to DSP pin muxing.
*------------------------------------------------------------------------------
*/

void GPMCPinMuxSetup(void)
{
/* GPMC_AD0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);

/* GPMC_AD1 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =
( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;

/* GPMC_AD2 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =
( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT);

/* GPMC_AD3 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =
( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT);

/* GPMC_AD4 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =
( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT);

/* GPMC_AD5 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =
( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT);

/* GPMC_AD6 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =
( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT);

/* GPMC_AD7 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =
( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT);

/* GPMC_CS2 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(2)) =
( 0 << CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE_SHIFT ) |
( 0 << CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN_SHIFT )|
( 0 << CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL_SHIFT )|
( 0 << CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE_SHIFT );

/* GPMC_OEN_REN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) =
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT ) |
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT ) |
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT);

/* GPMC_WEN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

// GPMC AA0
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

// GPMC AA1
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

// GPMC AA2
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

// GPMC AA3
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

}

- I Configured the code as per My Schematics.

- Here, the code reading and writing time the CS is not going to LOW.

Question:1  Is there any configuration is Missing for GPMC access?

Question:2  Please confirm me, the CS configuration is Correct or Not. What ever i am set base address (0x11000000) is correct here that is correct or not?

- DSP size is 16 MB.

Regards,

Vamsi.