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Starterware/AM3358: example of“uartEcho_edma” using uart4 does not work properly

Part Number: AM3358

Tool/software: Starterware

The example of “uartEcho_edma” using uart0 in starterware worked properly.

When I use uart2 instead of uart0,it does work properly.

But when I use uart4 instead of uart0,it does not work properly.There  seems no data received.

The changes of the code from uart0 to another uart:

UART_THR_RHR_REG,UART_INSTANCE_BASE_ADD,EDMA3_UART_TX_CHA_NUM,EDMA3_UART_RX_CHA_NUM,UART_INT_NUM

UART0ModuleClkConfig   to UART0_4ModuleClkConfig

the parameter of UARTPinMuxSetup

My English is terrible,I am sorry。

Where is the problem,can anybody help me?

  • Lei,
    Please take a look at this application note. Its not specific to the uartEcho_edma example, but will give an idea on what changes are needed in the code. Hope this helps.
    http://www.ti.com/lit/an/sprac32/sprac32.pdf 

    Lali

  • In reply to Lalindra Jayatilleke:

    Thank you for your response.

    The example of “uartEcho” using uart4 in starterware also worked properly.

    The changes of  example “uartEcho” from uart0 to uart4:

    SOC_UART_0_REGS to SOC_UART_4_REGS

    UART0ModuleClkConfig   to UART0_4ModuleClkConfig

    the parameter of UARTPinMuxSetup

    That is to say,the two function UARTPinMuxSetup(4) and  UART0_4ModuleClkConfig()  worked well in example uartEcho.This two function seems correct.

    But with addition changes of only some macro definitions metioned above,the example uartEcho_edma does not work.

  • In reply to lei lu:

    unsigned int UARTPinMuxSetup(unsigned int instanceNum)
    {
    unsigned int status = FALSE;

    if(0 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(instanceNum)) = 0x00000030;

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(instanceNum)) = 0x00000010;

    status = TRUE;
    return status;
    }
    else if(1 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(instanceNum)) = 0x00000030;

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(instanceNum)) = 0x00000010;

    status = TRUE;
    return status;
    }
    else if(2 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) = 0x00000031;

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) = 0x00000011;

    status = TRUE;
    return status;
    }
    else if(3 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS1) = 0x00000031;

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_ECAP0_IN_PWM0_OUT) = 0x00000011;

    status = TRUE;
    return status;
    }
    else if(4 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(0)) = 0x00000031;

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(0)) = 0x00000011;

    status = TRUE;
    return status;
    }
    else
    {
    return status;
    }

    }





    void UART0_4ModuleClkConfig(void)
    {
    /* Configuring L3 Interface Clocks. */

    /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |=
    CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE));

    /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |=
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /* Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |=
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL));

    /* Checking fields for necessary values. */

    /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */
    while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_IDLEST));

    /*
    ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
    CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to
    ** attain the desired value.
    */
    while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
    ** register to attain the desired value.
    */
    while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register
    ** to attain the desired value.
    */
    while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));


    /* Configuring registers related to Wake-Up region. */

    /* Writing to MODULEMODE field of CM_WKUP_CONTROL_CLKCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) |=
    CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
    CM_WKUP_CONTROL_CLKCTRL_MODULEMODE));

    /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) |=
    CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_L3_AON_CLKSTCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) |=
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL));

    /* Writing to MODULEMODE field of CM_WKUP_UART0_CLKCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) |=
    CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
    CM_WKUP_UART0_CLKCTRL_MODULEMODE));

    /* Verifying if the other bits are set to required settings. */

    /*
    ** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
    CM_WKUP_CONTROL_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));

    /*
    ** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_L4WKUP_CLKCTRL) &
    CM_WKUP_L4WKUP_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
    ** to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
    CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));

    /*
    ** Waiting for CLKACTIVITY_UART0_GFCLK field in CM_WKUP_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK));

    /*
    ** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_UART0_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_UART0_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
    CM_WKUP_UART0_CLKCTRL_IDLEST));




    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
    CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
    CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);






    /* Writing to MODULEMODE field of CM_PER_GPIO3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) |=
    CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
    CM_PER_UART1_CLKCTRL_MODULEMODE));



    /* Writing to MODULEMODE field of CM_PER_GPIO3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) |=
    CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
    CM_PER_UART2_CLKCTRL_MODULEMODE));


    /* Writing to MODULEMODE field of CM_PER_GPIO3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_UART3_CLKCTRL) |=
    CM_PER_UART3_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART3_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART3_CLKCTRL) &
    CM_PER_UART3_CLKCTRL_MODULEMODE));



    /* Writing to MODULEMODE field of CM_PER_GPIO3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_UART4_CLKCTRL) |=
    CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART4_CLKCTRL) &
    CM_PER_UART4_CLKCTRL_MODULEMODE));






    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK)));
    }
  • In reply to lei lu:

    The TI Starterware forum is now closed to new posts as Starterware is no longer a supported software offering. For more information about Starterware and migration, please see this FAQ. Since the functionality provided by Starterware is now included in TI's Software Development Kits (SDKs) for RTOS, the questions related to this functionality are now routed through the device forums (whose teams produce those SDKs).