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Related Posts

  • Forum Post: C6474 NDK running on each core MAC Address questions

    J. M.
    Hi, When I run the NDK on the 3 cores of the C6474 EVM, I see strange behavior. If I use the default hardcoded MAC addresses (00-01-02-03-04-05, 10-11-12-13-14-15, 21-22-23-24-25), I can ping the devices (after adding entries to the host PC arp table). However, when I use the EFUSED mac address (...
    on Aug 2, 2010

  • Forum Post: C6474 NDK running out of DDR on Cores 2 and 3

    J. M.
    Hello, I am having an issue getting the NDK to run out of DDR on cores 2 and 3 on a C6474 on a custom board. Each core has an exclusive partition of DDR2 for the .far:... NDK sections to run out of. There are no issues with Core 1. What I am seeing with Core 2 is that when I ping the address (correct...
    on Jan 13, 2011

  • Forum Post: IPC using MessageQ - what memory is used.

    Kerry Barnes
    I'm new to using the TI66678 and want to understand what memory is used by the MessageQ to communicate between processors. I understand there is a 4 Mbyte shared memory buffer on chip and then there is external DRAM. Is it possible to use either of these as the shared memory used by the MessageQ...
    on Sep 19, 2011

  • Forum Post: Data transfer between cores

    Andrey Savinkov
    Hi, platform TMX320C6678, IPC 1.22.05.27 sys/bios 6.31.04.27 ccs 5 C6678 device, little endian I try to send data array from Core0 to Core1, Core2 and Core3. I am creating a messageQ for intercore communication among the cores [CORE0, CORE1, CORE2, CORE3] of my 6678 board. I used the MessageQ...
    on Feb 14, 2012

  • Forum Post: JamaicaVM Personal Edition Free Download for embedded development with the Java programming language

    David Beberman
    aicas has made available JamaicaVM Personal Edition for free download available at www.aicas.com. Click on the link under the banner to be taken to the registration page. Personal Edition is a Linux host-only release of the complete toolchain. It is intended to be used for learning and experimentation...
    on Mar 11, 2012

  • Forum Post: Parallel computation with MessageQ

    Andrey Savinkov
    Hi, platform TMX320C6678, IPC 1.22.05.27 sys/bios 6.31.04.27 ccs 5 C6678 device, little endian I try to do parallel computing between CORE0, CORE1, CORE2 and CORE3. CORE0 is main core. It gets data from a sourse and send the data to other cores. My program like this: CORE0: for ...
    on Mar 14, 2012

  • Forum Post: Re: Codec Engine and Friends Blog

    OyvindV
    Hey, Chris, I have recently noticed that when trying to access the blog, I only get an error message saying: Not Found: Resource Not Found The resource you requested does not exist. Where did the blog go? :) This is also the case with the "Multicore Mix" blog. Can the...
    on Mar 15, 2012

  • Blog Post: BIOS-MCSDK 2.0.9: Maintenance update for C66x BIOS-MCSDK + C6657 support

    Raj Sivarajan
    BIOS MCSDK 2.0.9 is available for download ; this is a maintenance update for the production R2.0.0 release. This update can be manually downloaded or automatically downloaded directly from CCS using Eclipse Update Manager; see the BIOS MCSDK User's Guide for details on setting up automatic software...
    on Jun 12, 2012

  • Blog Post: BIOS-MCSDK 2.1.0 Beta Available for C66x DSP OpenMP Support

    Raj Sivarajan
    BIOS MCSDK 2.1.0 Beta is available for download . This release introduces OpenMP support for TMS320C6678. Note that this is a beta quality release; for the production quality release of C66X, see BIOS-MCSDK 2.0.9 . The major updates from the baseline release, BIOS MCSDK 2.0.9, are: OpenMP runtime...
    on Jun 30, 2012

  • Forum Post: Linux kernel deployment on c6678 DSP

    KBM
    Hi all, I am trying to deploy Linux kernel on the 8 cores of the C6678 DSP on my TMDXEVM6678L using the MAD tools with a Linux-c6x-2.0 kernel image (.bin). I am trying to followe the steps described in MCSDK Image Processing Demo Guide and MAD Utility Guide but it's seems that it's not the...
    on Jul 11, 2012

  • Blog Post: BIOS-MCSDK 2.1.0: OpenMP for C66x Multicore DSP

    Raj Sivarajan
    The production release of BIOS-MCSDK 2.1 is available for download . This release introduces OpenMP as a multicore programming methodology for TMS320C6678 and TMS320C6670. This release can be manually downloaded or automatically downloaded directly from CCS using Eclipse Update Manager; see the BIOS...
    on Sep 6, 2012

  • Forum Post: Problem trying to pass a pointer between cores and modify data using MessageQ

    Johannes
    (Please visit the site to view this file) (Please visit the site to view this file) Hi, platform evm 6678, IPC 1.24.3.32 sys/bios 6.33.6.50 ccs 5.1.0.09 I tried to modify the MessageQ example that comes with CCS/IPC to pass a pointer along with the message, then modify the value of data pointed...
    on Sep 12, 2012

  • Blog Post: BIOS-MCSDK 2.1.1: Maintenance update for C66x BIOS-MCSDK

    Raj Sivarajan
    BIOS MCSDK 2.1.1 is available for download ; this is a maintenance update for the production R2.1.0 release. This update can be manually downloaded or automatically downloaded directly from CCS using Eclipse Update Manager; see the BIOS MCSDK User's Guide for details on setting up automatic software...
    on Oct 6, 2012

  • Blog Post: BIOS-MCSDK 2.1.2: Maintenance update for C66x BIOS-MCSDK

    Raj Sivarajan
    BIOS MCSDK 2.1.2 is available for download ; this is a maintenance update for the production R2.1.0 release. This update can be manually downloaded or automatically downloaded directly from CCS using Eclipse Update Manager; see the BIOS MCSDK User's Guide for details on setting up automatic software...
    on Nov 13, 2012

  • Forum Post: Getting started on the TMS320C6678

    Friedrich Schick
    Hello, we are evaluating the TMS320C6678 for our image processing product. I ordered the TMDSEVM6678LE evaluation board, now its time to read some documentation. I wonder how to inter-communicate between all of the DSP-cores. My algorithm may be placed on the DSP core like the following. ...
    on Dec 6, 2012

  • Forum Post: receiving PCIe MSI interrupts as EP on C6657 using sysbios

    Weichun Yuan
    we are trying to use C6657 EVM to receive PCIe MSI interrupts (c6657 is configured as EP). I tried to write 0/8/16 to MSI_IRQ to trigger MSI to core 0 and test the MSI reception. But the isr is not triggered reliably. Most of the time, it is not hit (I had a global counter and also break point in isr...
    on Dec 6, 2012

  • Forum Post: Using mcoreloader for loading a application on core 1 to 7 and IPC

    Ajay Barboza
    1. I have set up linux c6x on core0. I want to write a application in which the core 1 sends message to the other cores about the data (pointer to the shared memory). 2. Also I suppose mcoreloader loads the same elf image on all 7 cores and I should use processor id to identify the IPC messages. How...
    on Feb 13, 2013

  • Blog Post: MCSDK 3.0 Beta Release Available for KeyStone II Devices

    Raj Sivarajan
    MCSDK 3.0 Beta is available for download . The MCSDK provides foundational software for TI KeyStone II device platforms. It encapsulates a collection of software elements and tools intended to enable customer application development and migration. The foundational components include: SYS/BIOS...
    on Apr 30, 2013

  • Blog Post: MCSDK 3.0 Production Release Available for KeyStone II Devices

    Raj Sivarajan
    MCSDK 3.0 production release is now available for download . This release provides foundational software for K2H and K2K KeyStone II devices. It encapsulates a collection of software elements and tools intended to enable customer application development. The foundational components include: ...
    on May 31, 2013

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