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SYS/BIOS Arm A15 Support

Other Parts Discussed in Thread: SYSBIOS

Hi experts;

As far as I know, For A15 Arm Processor only DRA7XX OMAP5430 devices have SYS/BIOS support. 

I am trying to understand what these "support" really means actually. I have a Keystone II evm which has 4 arm and 8 dsp core and i am trying to run sys/bios on these 4 arm core instead of linux. 

So what is the reason that although there is SYS/BIOS support for A-15 Core,  i am not able to use SYS/BIOS in keystone II architecture which have also A-15 core.

There may be some peripherals, timers ( device specific blocks ) which are used by SYS/BIOS in supported devices, but still I think the kernel, scheduler  should be same in all devices which have A-15 Core.  

So is it possible to configure SYS/BIOS to use it in all A-15 cores without considering the device ? 

here, there is an example for building SYSBIOS for A-15. I build this project in windows, but when i tried to load it to ARM core, i got the following error. 

http://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)

http://processors.wiki.ti.com/index.php/File:A15GccExampleWindows.zip

CortexA15_0: Trouble Writing Register PC: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 0.0.0.0)


CortexA15_0: Breakpoint Manager: Retrying with a AET breakpoint


CortexA15_0: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x80008984: (Error -1204 @ 0x3D5B) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 0.0.0.0)

Regards.

Tugrul

  • Hi Tugrul,

    Some of the peripheral base addresses on Keystone II are different from those on DRA7X/OMAP5430. For instance the GIC (Interrupt Controller) base addresses are different. By default, the Hwi module (Interrupt Controller Driver) gets added to every application and its startup code will generate an exception unless the base addresses are correct.

    You can add the following lines to your *.cfg script to fix the GIC Distributor and Controller Base addresses:

    var Hwi = xdc.useModule('ti.sysbios.family.arm.gic.Hwi');
    Hwi.gicdBaseAddress = 0x0256xxxx; // Please check your TRM to determine the exact base addresses
    Hwi.giccBaseAddress = 0x0256xxxx;

    If you have the MMU enabled (It is enabled by default), then you will also need to add entries for 0x0256xxxx to mark this region as Device Memory/Strongly Ordered. This is required to prevent a MMU fault.

    Link to MMU module cdoc which has some examples showing how to add MMU entries:

    http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_35_03_47/exports/bios_6_35_03_47/docs/cdoc/index.html#ti/sysbios/family/arm/a15/Mmu.html

    The default timer module used by DRA7X and OMAP5430 uses the A15 Generic Timers. This timer module uses CP15 instructions to program the timer so there are no base addresses to deal with here. You do need to set the right timer frequency though. The Timer.intFreq config param in specific needs to be set: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_35_03_47/exports/bios_6_35_03_47/docs/cdoc/index.html#ti/sysbios/family/arm/systimer/Timer.html#int.Freq

    On DRA7X and OMAP5430 the A15 Generic Timers have an effective frequency of 6.144 MHz. I believe on Keystone II the frequency is different. You need to worry about this only if you plan to use timers or leverage the SYS/BIOS clock which internally uses these timers. Also, please note that SYS/BIOS only supports non-secure mode so if the A15 is in secure mode, you need to change the security mode to non-secure first. This can be done using the gel script in CCS or in the bootloader.

    If you build the application with the above changes, I would expect it to run fine.

    As for the errors that you get at load time. Can you open Tools->ARM Advanced features and check if the MMU is enabled when you load your app ? You want to disable the MMU, Data and Instruction cache before loading your app.

    Best,

    Ashish

  • Hi Ashish;

    Thank you for your detailed answer. After I post the message, I tried to init the board by using a .gel file before loading the out file. It seems i solved the connection problem. ( when try to load ARM tries to access DDR, and also pll is not initialized )

    I am not familiar with ARM processors but I tried to debug it. When I loaded it, Program Counter could not come to main. When I deasassembly it, and proceed through _c_int, I noticed it stuck somewhere related with xds functions. 

    Now, I will try your suggestions then  I will inform you. Thanks

    Tugrul

  • Hi Tugrul,

    tugrul mutlu said:

    After I post the message, I tried to init the board by using a .gel file before loading the out file. It seems i solved the connection problem. ( when try to load ARM tries to access DDR, and also pll is not initialized )

    Looks like the memory controller (EMIF) is not initialized. One way is to run some gel script to do all the required board init. But, I am not sure where to get the right gel scripts for Keystone II. You may want to check on the Keystone forum. An alternative is to run uboot and let it do the board init. Here's a wiki page that explains how to run uboot from CCS:

    http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Tools#Loading_and_Running_U-Boot_using_CCS

    Best,

    Ashish

  • Hi Ashish;

    I update .cfg file as you suggested. I attached it. I added the lines below. 

    var Hwi = xdc.useModule('ti.sysbios.family.arm.gic.Hwi');
    Hwi.gicdBaseAddress = 0x02561000;
    Hwi.giccBaseAddress = 0x02564000;

    Actually I am not sure about these values.Here I paste the pictures where i got these values. 

    These picture is from Cortex A-15 TRM. I got 0x1000 for distributor & 0x4000 for controller.( ?)

    These one is from KeyStone II memory Map. This line is the only related one with GIC. There is no Distributor or Controller Base Addres.

    I also check A-15 Generic Timers frequency for Keystone II but I couldnt found any information about it.. 

    After I connect the ARM with the emulator, I check the MMU. It seems it is disabled. 


    With these configuration, I load the out file. When I run it, an exeption occured. I copy&paste it here. 

    Exception occurred in ThreadType_Main.
    Main handle: 0x0.
    Main stack base: 0x900122e8.
    Main stack size: 0x1000.
    R0 = 0x40000000 R8 = 0x00008030
    R1 = 0x00000001 R9 = 0xffffffff
    R2 = 0x00000006 R10 = 0x00000000
    R3 = 0x00000004 R11 = 0x00000002
    R4 = 0x0000000f R12 = 0x000001df
    R5 = 0x0000001c SP(R13) = 0xfffff910
    R6 = 0x00000001 LR(R14) = 0x9000ad70
    R7 = 0xffffffff PC(R15) = 0x90000a90
    PSR = 0x600001df
    ti.sysbios.family.arm.exc.Exception: line 180: E_undefinedInstruction: pc = 0x90000a90, lr = 0x9000ad70.
    xdc.runtime.Error.raise: terminating execution

    This error occured in _c_int functions. I deassembly it and found where the error is. I copy&paste it here.

    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))

    @ enable access to cp10 and cp11
    @ required for SIMD and VFP to work


    movw r0, #0x0000
    movt r0, #0x00F0
    mcr p15, #0, r0, c1, c0, #2
    isb

    @ set the FPEXC.EN bit to enable Advanced SIMD and VFP
    movw r0, #0x0000
    movt r0, #0x4000
    fmxr fpexc, r0 @ gcc does not support UAL equivalent
    @ instruction, vmsr
    #endif

    These code is from boot.asm. The error occurs when the PC comes to the red line. I think this instruction is something about floating point operations . I am not sure about it. 

    I attached my .cfg file here. Thank you for your help..

    3404.sysbios.cfg 

    Regards

    Tugrul

  • Hi Tugrul,

    The gicdBaseAddress of 0x02561000 is ok but giccBaseAddress should be 0x02562000.

    tugrul mutlu said:

    movw r0, #0x0000
    movt r0, #0x00F0
    mcr p15, #0, r0, c1, c0, #2
    isb

    @ set the FPEXC.EN bit to enable Advanced SIMD and VFP
    movw r0, #0x0000
    movt r0, #0x4000
    fmxr fpexc, r0 @ gcc does not support UAL equivalent
    @ instruction, vmsr
    #endif

    This instruction enables Hardware Floating-Point instructions. Since Keystone has a HW FPU I would expect it to work. I have a few questions. Is the A15 running in non-secure mode ? Also, how did you init the board - using uboot or some other way ?

    If the A15 is in non-secure mode, then FPEXC can only be accessed if NSACR (Non-secure access control register) is configured to allow non-secure mode access to CP10 & CP11 coprocessors. If you are using uboot for board init, I would expect it to setup the NSACR correctly.

    Best,

    Ashish

  • Hi Ashish;

    Sory for the late reply because of the weekend. 

    I init the board with a .gel file. Because this gel file only work with KeyStone II 6638 DSP Cores, first I connect one of the DSP Core, then continue to load the program to ARM Core. This is the way how I am trying to init the board. 

    After your post I checked the working mode of ARM. It was working in non-secure mode. I realized that when I changed the mode to secure, FPEXC instruction is not a porblem anymore. But now when I ran, it still stuck some where else in _c_int00 function. 

    As your suggestion, now I am trying to init the board with uboot. First I run uboot java scripts, then try to load the program to ARM with CCS. But there is something wrong with this way because PC is not going _c_int. Now I am trying to figure out this. 

  • Hi Tugrul,

    Attached please find the gel script that I use to put the A15 into non-secure mode (I have changed the GIC base addresses to match Keystone II spec but just double check they are correct). It does all the necessary GIC and NSACR configuration before changing the security mode.

    2117.ChangeSecurityMode.gel

    Once you run uboot, I expect the system to still be in secure mode. Run the above script to put it in non-secure mode.

    Best,

    Ashish

  • Hi Ashish;

    Great news..

    All modules are initiated properly, and PC goes to main. But in order to do that I need to change the settings in ARM Advanced Features.

    First I realize that .gel script is not changing the related registers ( SCR, NSARC) So when I run it, it gives an exeption(Undefined Instruction Exeption) But when I change Security Enabled Field ( tools- ARM Advanced Features;   I need to click on it several times)  it works. 

    Still there is something I am missing about security mode. Now I am trying to figure out this. 

    Regards

    Tugrul

  • Hi Tugrul,

    Thats great!

    Did you try using the gel script I shared in my previous post for putting the A15 in non-secure mode ? And what are the question you still have about security mode ?

    Best,

    Ashish

  • Hi Ashish;

    I think I solved the problem. I init the device with uboot. But I dont boot it with using it. I just stop uboot, then try to load the program using CCS. In MCSDK user guide it said that after uboot, monitor code need to be installed. So before loading my program, i run mon_install command in uboot command line. 

    Then I realize that uboot run in thumb mode ( 16 bit instruction) So in order to change it  to ARM mode ( 32 bit), I wrote a .gel file which change the CPRS register. After that, when I run it, it perfectly works.

    I am really appreciated for your help.. 

    Regards

    Tugrul

  • Hi Ashish;

    Actually I wonder, which OS do you suggest to use in ARM, SYS/BIOS or Linux ?  & Why ?

    It is an LTE-A project. 

    Regards

    Tugrul 

  • Hello,

    I've had the same problem solved Diasbling MMU and Cache from Advanced ARM menu.

    Is there a way to insert these steps in the GEL file?

    Thanks in advance.

  • Hi LucaM,

    What device/board are you working on ? Assuming you are on a A15, here's some gel code to disable the MMU and Caches. This code should work on Keystone II, OMAP5 and DRA7XX:


    #define MMU_ON 0x1 #define MMU_OFF ~MMU_ON hotmenu Disable_MMU() { int status; GEL_TextOut("Disabling MMU\n"); status = REG_CTXA15_CP15_C1_SCTLR; status &= MMU_OFF; REG_CTXA15_CP15_C1_SCTLR = status; } #define ICACHE_ON 0x1000 #define ICACHE_OFF ~ICACHE_ON #define DCACHE_ON 0x4 #define DCACHE_OFF ~DCACHE_ON hotmenu Disable_Caches() { int status; GEL_TextOut("Disabling Caches\n"); status = REG_CTXA15_CP15_C1_SCTLR; status &= DCACHE_OFF; status &= ICACHE_OFF; REG_CTXA15_CP15_C1_SCTLR = status; // invalidate entire instruction cache GEL_TextOut("Invalidate Instruction Caches\n"); REG_CTXA15_CP15_C7_ICIALLU = 1; return; }

    If you plan to load apps back to back using CCS, I would recommend power cycling the board in between. This is because of the way the cache behaves.


    Also, I have another request. Please start a new thread for a fresh question in the future. If a thread has been answered and closed sometime back, we stop tracking it and your question may get ignored.

    Thanks,

    Ashish

  • Hi Ashish,

    I work with Sitara AM335x famly. Is the same the gel modification?

    Sorry for the post-place.

    Thanks.

  • Hi LucaM,

    For AM335x the gel code is a bit different as it has Cortex-A8 instead of Cortex-A15. Here's an example:

    #define ICACHE_ON 0x1000
    #define ICACHE_OFF ~ICACHE_ON
    #define DCACHE_ON 0x4
    #define DCACHE_OFF ~DCACHE_ON
    
    hotmenu Disable_Caches()
    {
        int status;
    
        status = CP15_CONTROL_REGISTER;
        status &= DCACHE_OFF;
        status &= ICACHE_OFF;
        CP15_CONTROL_REGISTER = status;
    }
    
    #define MMU_ON 0x1
    #define MMU_OFF ~MMU_ON
    
    hotmenu Disable_MMU()
    {
        int status;
    
        status = CP15_CONTROL_REGISTER;
        status &= MMU_OFF;
        CP15_CONTROL_REGISTER = status;
    }

    Best,

    Ashish