AMMU Configuration for IPU on DRA7xx

Hi Mesut,

Yes, the AMMU can be configured from the SYSBIOS .cfg file. In the IPC 3.x product, we configure the AMMU in all of the examples. The 'ex02_messageq' example would be a good one to take a look at.

Best regards,

Vincent

Hi Vincent,

thanks for the fast respond, I was aware of the IPC examples but unfortunately I could not get up running with the AMMU configuration from the *cfg files.

By the examples I am missing also the A15 initialization from the IPU are you doing this with gel files?

Could be that the *.gel files doing some first initialization from the AMMU?

And additional the Info from TRM sounds for me that the configuration from AMMU  shall be done before the IPU is released from reset.

 

DRA75x, DRA74x

Infotainment Applications Processor

Silicon Revision 1.

Version N

3.5.6.10 IPU1 Subsystem Power-On Reset Sequence

1…

4. MPU software must configure CACHE_MMU_IPU once CACHE_MMU_IPU is out of reset. After

CACHE_MMU_IPU configuration and cache initialization is done, MPU software clears the

RM_IPU1_RSTCTRL[0] RST_CPU0 bit in the PRCM module register

6..

 

Kind regards

Mesut

Hi Mesut,

Are you running SYSBIOS on the A15? If so, you should take a look at the ex11_ping example under <IPC_INSTALL_DIR>/examples/DRA7XX_bios_elf. This example is meant to run in an all-BIOS configuration where the host is running SYSBIOS. Here is the procedure for loading and running the example:

1. Power up VayuEVM, press PWR RESET button

2. Connect CCS to IcePick

3. Select Scripts > IcePick Utility > System Reset from CCS menu

4. Connect to CortexA15_0

5. Select Scripts > DRA7xx MULTICORE Initialization > DSP1SS_ClkEnable_API from CCS menu

6. Connect to DSP1

7. Reset DSP1

8. Select CortexA15_0, repeat 5 – 7 for each core (non-EVE) that you use. For IPUs, you would also need to right-click on the IPU in the Debug Window, select Open GEL Files View, Then in the GEL Files view, right-click on it and select Load GEL to load the GEL file in ex11_ping\ipu1-0 (or ipu2 depending on the IPU you are trying to connect to). This GEL file does a minimal AMMU setup so that the loader can access the memory it needs to load.

After loading the GEL file, run the GEL function under Scripts->ex11_ping->ex11_ping_ipu1-0_ammu_config in the CCS menu in order for the AMMU programming to take effect.

If using EVE, go through steps 9-12. Otherwise skip to 13. 

9. Select CS_DAP_DebugSS

10. GEL Files > Load Gel... > eve1/ex11_ping_eve1.gel

11. Scripts > EVE MMU Configuration > ex11_ping_eve1_mmu_config

12. Repeat 9 – 11 for each eve you are using

 

13. Load each processor

14. Run CortexA15_0 (must always run this core first before other slaves)

15. Run each core to main (optional, just to ensure this much is working)

16. Run all cores (start them one at a time)

17. Wait 3 seconds

18. Halt all cores (including A15 if you like)

19. Select DSP1

20. Open ROV

21. Look at LoggerBuf records. Last one should say 'Done'

22. Repeat 19 – 21 for all other cores.

I believe the GEL file in step 8 may be what you are missing. You would need to customize it for your program to give the CCS loader access to the memory it is loading. When the IPU starts to run, it will then reconfigure the AMMU according to the settings in the .cfg file.

Best regards,

Vincent

Hi Vincent,

Thanks for the detailed description.

But we are using our own Hardware which has QNX on A15  and SYSBIOS running on M4  what I did in the moment is I configured the AMMU from  A15 by  "IPL"  startup code .

My question was if is possible to do the AMMU configuration on the M4 SYSBIOS over cfg file or over startup hook function.  

what you describe is you are using the gel files to do the configuration which I took as template and did on QNX side see code under.

But My Intention is to do this only from M4 side because I want not have such dependences on QNX A15 side.

The same I did on J5eco “TI814x “   and this works just with SYSBIOS *.cfg configuration.

 

Best regards
 Mesut

   /*

    * CM_IPU1_CLKSTCTRL  0x4A005500

    *

    * 1:0 CLKTRCTRL Controls the clock state transition of the BELLINI0 clock      RW 0x3

    *    domain.

    *  0x0: NO_SLEEP: Sleep transition cannot be initiated.

    *       Wakeup transition may however occur.

    *  0x1: SW_SLEEP: Start a software forced sleep transition

    *       on the domain.

    *  0x3: HW_AUTO: Automatic transition is enabled. Sleep

    *       and wakeup transition are based upon hardware

    *       conditions.

    *  0x2: SW_WKUP: Start a software forced wake-up

    *       transition on the domain.

    */

      out32(CM_IPU1_CLKSTCTRL, 0x2);

 

 

   /* Enable benelli clocks

    * CM_IPU1_IPU1_CLKCTRL   0x4A005520

    *

    * 24 CLKSEL Selects the timer functional clock RW 0x0

    *    0x0: Selects DPLL_ABE_X2_CLK as the functional clock

    *    0x1: Selects CORE_IPU_ISS_BOOST_CLK as the

    *         functional clock

    * 1:0 MODULEMODE Control the way mandatory clocks are managed. RW 0x0

    *    0x0: Module is disabled by SW. Any OCP access to

    *         module results in an error, except if resulting from a

    *         module wakeup (asynchronous wakeup).

    *    0x1: Module is managed automatically by HW according

    *         to clock domain transition. A clock domain sleep

    *         transition put module into idle. A wakeup domain

    *         transition put it back into function. If CLKTRCTRL=3, any

    *         OCP access to module is always granted. Module clocks

    *         may be gated according to the clock domain state.

    *    0x3: Reserved

    *    0x2: Reserved

    */

      out32(CM_IPU1_IPU1_CLKCTRL, 0x01000001);

 

   /* Reset asserted for IPU CPU0, CPU1, Unicache and MMU

    * RM_IPU1_RSTCTRL  0x4AE06510

    *

    * 2 RST_IPU BELLINI system reset control. RW 0x1

    *   0x0: Reset is cleared for IPU CACHE MMU

    *   0x1: Reset is asserted for the IPU CACHE MMU

    * 1 RST_CPU1 BELLINI Cortex M4 CPU1 reset control RW 0x1

    *   0x0: Reset is cleared for the IPU Cortex M4 CPU1

    *   0x1: Reset is asserted for the IPU Cortex M4 CPU1

    * 0 RST_CPU0 BELLINI Cortex M4 CPU0 reset control. RW 0x1

    *   0x0: Reset is cleared for the IPU Cortex M4 CPU0

    *   0x1: Reset is asserted for the IPU Cortex M4 CPU0

    */

   out32(RM_IPU1_RSTCTRL, 0x7);

 

   /* Reset deassertion for IPU Unicache/MMU

    * RM_IPU1_RSTST   0x4AE06514

    *

    * 2 RST_IPU IPU system SW reset status RW 0x0

    *   0x0: No SW reset occurred

    *   0x1: IPU MMU and CACHE interface has been reset

    *        upon SW reset

    * 1 RST_CPU1 BELLINI Cortex-M4 CPU1 SW reset status RW 0x0

    *   0x0: No SW reset occurred

    *   0x1: Cortex M3 CPU1 has been reset upon SW reset

    *

    * 0 RST_CPU0 BELLINI Cortex-M4 CPU0 SW reset status RW 0x0

    *   0x0: No SW reset occurred

    *   0x1: Cortex M3 CPU0 has been reset upon SW reset

    */

   out32(RM_IPU1_RSTST, 0x7);

 

 

   out32(RM_IPU1_RSTCTRL, 0x3);

 

 

    /* RM_IPU1_RSTST  0x4AE06514

     2 RST_IPU IPU system SW reset status RW 0x0

       0x0: No SW reset occurred

       0x1: IPU MMU and CACHE interface has been reset

       upon SW reset

     1 RST_CPU1 BELLINI Cortex-M4 CPU1 SW reset status RW 0x0

       0x0: No SW reset occurred

       0x1: Cortex M4 CPU1 has been reset upon SW reset

     0 RST_CPU0 BELLINI Cortex-M4 CPU0 SW reset status RW 0x0

       0x0: No SW reset occurred

       0x1: Cortex M4 CPU0 has been reset upon SW reset

     */

    while ((in32(RM_IPU1_RSTST) & 0x4) != 0x4);

 

 

    /*---------------- Setup the UNICACHE MMU -----------------*/

    /*Large Page Translations */

    /* Logical Address */

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x800;

    out32(regAddr,         0x40000000); regAddr += 0x4;

    out32(regAddr,         0x80000000); regAddr += 0x4;

    out32(regAddr,         0xA0000000); regAddr += 0x4;

    out32(regAddr,         0x60000000); regAddr += 0x4;

 

    /* Physical Address */

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x820;

    out32(regAddr,         0x40000000); regAddr += 0x4;

    out32(regAddr,         0x80000000); regAddr += 0x4;

    out32(regAddr,         0xA0000000); regAddr += 0x4;

    out32(regAddr,         0x40000000); regAddr += 0x4;

 

    /* Policy Register */

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x840;

    out32(regAddr,         0x00000007); regAddr += 0x4;

    out32(regAddr,         0x000B0007); regAddr += 0x4;

    out32(regAddr,         0x00020007); regAddr += 0x4;

    out32(regAddr,         0x00000007); regAddr += 0x4;

 

    /*Medium Page*/

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x860;

    out32(regAddr,         0x803F0000); regAddr += 0x4;

    out32(regAddr,         0x00400000); regAddr += 0x4;

 

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x8A0;

    out32(regAddr,         0x40300000); regAddr += 0x4;

    out32(regAddr,         0x40400000); regAddr += 0x4;

 

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x8E0;

    out32(regAddr,         0x00000007); regAddr += 0x4;

    out32(regAddr,         0x00020007); regAddr += 0x4;

 

    /*Small Page*/

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x920;

    out32(regAddr,         0x00000000); regAddr += 0x4;

    out32(regAddr,         0x40000000); regAddr += 0x4;

    out32(regAddr,         0x00004000); regAddr += 0x4;

    out32(regAddr,         0x00008000); regAddr += 0x4;

    out32(regAddr,         0x20000000); regAddr += 0x4;

 

    regAddr = IPU1_MMU_CFG;

    regAddr += 0x9A0;

    out32(regAddr,         0x55020000); regAddr += 0x4;

    out32(regAddr,         0x55080000); regAddr += 0x4;

    out32(regAddr,         0x55024000); regAddr += 0x4;

    out32(regAddr,         0x55028000); regAddr += 0x4;

    out32(regAddr,         0x55020000); regAddr += 0x4;

 

    regAddr = IPU1_MMU_CFG;

    regAddr += 0xA20;

    out32(regAddr,         0x0001000B); regAddr += 0x4;

    out32(regAddr,         0x0000000B); regAddr += 0x4;

    out32(regAddr,         0x00010007); regAddr += 0x4;

    out32(regAddr,         0x00000007); regAddr += 0x4;

    out32(regAddr,         0x00000007); regAddr += 0x4;

Hi Vincent

I know this is an old post,

I am trying to import this project into CCS5. The build is broken early.
I did set paths in the products.mak as fas as I can tell.
But I get some include files can not be open.

I am assuming the makefiles are OK, just we need to add the various paths according to individual installations.
Would please share just the changes you made on all makefiles in this project so that I can build it myself.

Regards

Can you please open a new thread and reference this thread? It makes managing forum posts much easier for us.

Thanks,
Todd

Sorry about that. Done

But not sure what I should do with this thread now.