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Fail to enable L2 cache of C66x DSP of Vayu

Dong Yang
Expert 5210 points

Expert 

I modified  dce_dsp.cfg from folder 'ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/platform/ti/dce/baseimage/' to enabled L1 and L2 cache. Then I check register L1PCFG(0x01840020h),   L1PCFG(0x01840040h), and  L2CFG(0x01840040h) to verified cached status.  I found L1P and L1D are cachable.  L2 cache is still uncached.  Can you help check anything i'm missing.

var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
/*Cache.setMarMeta(0xa0000000, 0x02000000, Cache.Mar_DISABLE);*/
Cache.setMarMeta(0x80000000, 0x00100000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);
var L1cache = new Cache.Size();
L1cache.l1dSize = Cache.L1Size_32K;
L1cache.l1pSize = Cache.L1Size_32K;
L1cache.l2Size = Cache.L2Size_256K;

I have post the issue in internal forum as following

https://e2e.ti.com/support/omap/int_omap/f/941/t/352882.aspx

  • 0
    TI__Mastermind 37985 points

    Can you post the command line output for your build? I would like to see if there are any warning coming from the configuration step, and also which platform you are using. A possible cause of the problem you are seeing is that the RTSC platform allocated all of L2 memory as SRAM, which means that the generated linker command line will allow linker to allocate sections to SRAM. Then SYS/BIOS won't let you use that same memory as cache.

  • 0 in reply to Sasha Slijepcevic
    TI__Expert 5210 points

    Sasha

    Thanks for your reply.

    Here is compile logs.  We are refere vayu platform.

    BR

    Dong8306.compile_log.txt

  • 0 in reply to Dong Yang
    TI__Mastermind 37985 points

    Dong,
    I couldn't really see what I hoped to see in the output. I wanted to see the location of the file config.bld that you are using to build you image. That file and the file package.bld, which should be located in /home/dong/glsdk/ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/platform/ti/dce/baseimage define which platform is used to build your image and how is its memory map configured.

    If you look into package.bld, there should be a call to addExecutable, and the third parameter of that call is the name of the platform. That same name is used in config.bld to define the memory map.

    You could probably open the file .xdcenv.mak in /home/dong/glsdk/ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/platform/ti/dce/baseimage, and you would find a reference to config.bld in there.

    I guess if you post these two files, I could make further suggestions.

  • 0 in reply to Sasha Slijepcevic
    TI__Expert 5210 points

    Sasha

    Thanks for your prompt response.

    Here is config.bld and .xdcenv.mak  zip file

    2018.baseimage.zip

    BR

    Dong

  • 0 in reply to Dong Yang
    TI__Mastermind 37985 points

    Your config.bld is /home/dong/glsdk/ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/build/config.bld, and I don't see it in the zip file you attached.
    The platform you are using for C66 seems to be the default platform "ti.platforms.simTCI6616", but I need to see config.bld to be sure.

  • 0 in reply to Sasha Slijepcevic
    TI__Expert 5210 points

     Sasha

    I am able to enable L1 and L2 cache in GLSDK by following modification.  Register L2CFG (offset: 0x01840000h) indicates L2Cache is 256K.  I also test performance with Han tao’s project.  Performance is 10x comparing to L2 cache disabled.  Is it the righ place to set L2 cache. Here is bld file.  7167.config_bld.7z

    1. Change Mar as following in ‘ xx/ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/platform/ti/dce/baseimage/dce_dsp.cfg’

    /*Cache.setMarMeta(0xa0000000, 0x02000000, Cache.Mar_DISABLE);*/

    Cache.setMarMeta(0xa0000000, 0x02000000, 0xD);

     

    1. add three red lines of code to  config.bld  as below in ‘xx/ti-glsdk_dra7xx-evm_6_03_00_01/component-sources/dspdce_1_00_00_01/build/config.bld’

    Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {

            externalMemoryMap: [

                    [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp1.EXT_CODE ],

                    [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp1.EXT_DATA ],

                    [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp1.EXT_HEAP ],

                    [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp1.TRACE_BUF ],

                    [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp1.EXC_DATA ],

                    [ "PM_DATA", evmDRA7XX_ExtMemMapDsp1.PM_DATA ]

            ],

            codeMemory: "EXT_CODE",

            dataMemory: "EXT_DATA",

            stackMemory: "EXT_DATA",

            l1PMode: "32k",

        l1DMode: "32k",

        l2Mode:  "256k"

    };

  • 0 in reply to Dong Yang
    TI__Mastermind 37985 points

    Yes, that last red line in config.bld is what makes L2 cache available. So, it seems your app is now working as expected. If so, can you please close the thread?

  • 0 in reply to Sasha Slijepcevic
    TI__Expert 5210 points

    Sasha

    Yes. it can be closed.  Can you help to look into following issue?

    https://e2e.ti.com/support/embedded/int-embedded_software/int-bios/f/123/t/354829.aspx

    BR

    Dong