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Grace 3.0 Timer interval miscalculated when using timer divisor

Mike Mitchell1
Intellectual 960 points

When using Interval mode and a timer clock source divisor, it seems that Grace 3.0 miscalculates the interval. 

ACLK=8192 Hz, Desired Interval=200 mS, Clock Divisor=4. 

Generated Code:

TIMER_A_configureUpMode(TIMER_A1_BASE, TIMER_A_CLOCKSOURCE_ACLK, TIMER_A_CLOCKSOURCE_DIVIDER_4,
1637, TIMER_A_TAIE_INTERRUPT_DISABLE, TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE, TIMER_A_SKIP_CLEAR);

-----------------------------------------------

Timer1_A3.timerMode = xdc.module("ti.mcu.msp430.csl2.timer.ITimer").IntervalMode;
Timer1_A3.intervalModeActive = true;
Timer1_A3.compareValue[0] = 101;
Timer1_A3.regs.interruptSource[1].interruptEnable = true;
Timer1_A3.regs.interruptSource[1].interruptHandler = true;
Timer1_A3.intervalModeAdvanced = true;
Timer1_A3.TACTL.timerClockSourceDivider = xdc.module("ti.mcu.msp430.csl2.timer.ITimer_A").TIMERA_CLOCKSOURCE_DIVIDER_4;
Timer1_A3.regs.interruptSource[0].interruptHandler = true;
Timer1_A3.regs.interruptSource[2].interruptHandler = true;
Timer1_A3.regs.interruptSource[3].interruptHandler = true;

Timer1_A3.inputClockToTimer = 8.192;

Timer1_A3.intervalDesiredPeriod = 200.0;
Timer1_A3.pwmDesiredFrequency = 5.0;

  • 0
    TI__Intellectual 1560 points

    Bug 3024 Timer interval miscalculated when using timer divisor has been submitted. This will be resolved in Grace 3.00.01.

    I believe you can work around this by setting the Divider before setting the Desired Interval  Period.

    Regards,

    Joe