Using tirtos_c6000_2_00_01_23, which contains bios_6_40_01_15 a custom platform was created for a TMS320C6678 in which the L2 cache size was set to the maximum of 512K for the TMS320C6678.
On core 0 the L2CFG register at 0x1840000 contained the value 0x07000005 meaning a L2MODE value of 5 =512K. i.e. the L2 cache size had been set to the requested value.
However, a call to Cache_getSize() returned a l2size of ti_sysbios_family_c66_Cache_L2Size_256K.
The problem is that the Cache_getSize function in tirtos_c6000_2_00_01_23\products\bios_6_40_01_15\packages\ti\sysbios\family\c66\Cache.c has an incorrect upper limit of 256K:
/*
* ======== Cache_getSize ========
* Returns the L1D, L1P, and L2 cache sizes.
* If value of L2 size is greater than Cache_L2_256K then return
* Cache_L2_256K.
* If value of L1 size is greater than Cache_L1_32K then return
* Cache_L1_32K.
*/
Void Cache_getSize(Cache_Size *size)
{
UInt tmpSize;
/*
* Read the L2 CFG register
* Its possible the register value is greater than 4 in which case
* we simply return 4 since values greater than 4 is equivalent to 4.
*/
tmpSize = *L2CFG & L2CFG_MODE_MASK;
if (tmpSize > Cache_L2Size_256K) {
tmpSize = Cache_L2Size_256K;
}
size->l2Size = (Cache_L2Size)tmpSize;
For a c66 device the maximum L2 cache size allowed for should be increased to Cache_L2Size_1024K (6)
