We are porting Am335x StarterWare drivers to SysBios 6.40.01.15 using CCS6.. After a lot of troubleshooting why StarterWare examples were not working in SysBios, we discovered that DDR3 cache was configured for write-back mode in SysBios:
var attrs_cacheable = { // write-back
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: true;
cacheable: true,
When we switched to write-through mode, everything started working:
var attrs_cacheable = { // write-through
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: false,
cacheable: true,
Apparently we were cacheing buffers or registers without actually writing anything. This thread was useful: http://e2e.ti.com/support/embedded/tirtos/f/355/t/289702.aspx
Questions:
1. Where are Am335x cache parameters bufferable, cacheable, and shareable documented? I don't see anything in Am335x TRM about the MMU.
2. Which registers can we display at runtime to verify cache settings?
3. How do global settings for bufferable & cacheable in SysBios example (ti.sysbios.family.arm.a8.mmu) correspond to separate initializations for Inner and Outer cache in StarterWare? Does Inner mean L1 and Outer L2?
4. What is Tex shown in the ti.sysbios.family.arm.a8.mmu example?
5. Where is the GUI documented for "A8 MMU - Module Settings" (Section, Tex, Implementation Defined, Domain Access Control, Access permission)? The question mark links to "Sys/Bios top-level manager" instead of a section for MMU.