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SysBios Am335x cache

Other Parts Discussed in Thread: SYSBIOS

We are porting Am335x StarterWare drivers to SysBios 6.40.01.15 using CCS6..  After a lot of troubleshooting why StarterWare examples were not working in SysBios, we discovered that DDR3 cache was configured for write-back mode in SysBios:

var attrs_cacheable = { // write-back
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: true;
cacheable: true,

When we switched to write-through mode, everything started working:

var attrs_cacheable = { // write-through
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: false,
cacheable: true,

Apparently we were cacheing buffers or registers without actually writing anything.  This thread was useful:  http://e2e.ti.com/support/embedded/tirtos/f/355/t/289702.aspx

Questions:

1. Where are Am335x cache parameters bufferable, cacheable, and shareable documented?  I don't see anything in Am335x TRM about the MMU.

2. Which registers can we display at runtime to verify cache settings?

3. How do global settings for bufferable & cacheable in SysBios example (ti.sysbios.family.arm.a8.mmu) correspond to separate initializations for Inner and Outer cache in StarterWare?  Does Inner mean L1 and Outer L2?

4. What is Tex shown in the ti.sysbios.family.arm.a8.mmu example?

5. Where is the GUI documented for "A8 MMU - Module Settings" (Section, Tex, Implementation Defined, Domain Access Control, Access permission)?  The question mark links to "Sys/Bios top-level manager" instead of a section for MMU.

  • Write-through mode seems to show no performance increase over cache disabled.  Can somebody point me toward a working example of SysBios running on Am335x with DDR3 cache enabled?

  • henlee said:

    1. Where are Am335x cache parameters bufferable, cacheable, and shareable documented?  I don't see anything in Am335x TRM about the MMU.

    The parameters can be found in the ARM Architecture Reference Manual (you need to create an account to view the document): http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html

    See the section named: Short-descriptor format memory region attributes, without TEX remap

    henlee said:

    2. Which registers can we display at runtime to verify cache settings?

    You can use ROV to view the MMU sections and options at runtime.

    henlee said:

    3. How do global settings for bufferable & cacheable in SysBios example (ti.sysbios.family.arm.a8.mmu) correspond to separate initializations for Inner and Outer cache in StarterWare?  Does Inner mean L1 and Outer L2?

    The SYS/BIOS manages the ARM core (Cache, MMU, Hwi, etc) and should be the only mechanism managing the Cache and MMU.  Do not mix Starterware Cache/MMU APIs with SYS/BIOS.  However, Starterware peripheral APIs can still be used (UART/SPI/I2C/PWM/etc..).

    henlee said:

    4. What is Tex shown in the ti.sysbios.family.arm.a8.mmu example?

    TEX is an ARM memory region attribute, please see ARM manual for more details.

    henlee said:

    5. Where is the GUI documented for "A8 MMU - Module Settings" (Section, Tex, Implementation Defined, Domain Access Control, Access permission)?  The question mark links to "Sys/Bios top-level manager" instead of a section for MMU.

    MMU support can be found in the Device Support tab (Top row of options).  The MMU page will allow you to set MMU sections defaults.  The GUI does not provide a means to create/modify a particular section, MMU sections need to manually be created in the .cfg file.

    Regards,

    -- Emmanuel

  • It is working now.  I dumped the MMU table for StarterWare and configured cache for DDR3 & I/O ports the same way in SysBios.  Very helpful answer, Emmanuel.  Thanks.