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[AM335x SYSBIOS/Starterware] The Cache configuration for the device memory (SD cardH)

Other Parts Discussed in Thread: SYSBIOS

Hi all,

  Now I am writing a code to use the SD card to load the firmware, but not use the DMA.

  The MMU configuration is as below:

void MMUConfigAndEnable(void)
{
    /*
    ** Define DDR memory region of AM335x. DDR can be configured as Normal
    ** memory with R/W access in user/privileged modes. The cache attributes
    ** specified here are,
    ** Inner - Write through, No Write Allocate
    ** Outer - Write Back, Write Allocate
    */
    REGION regionDdr = {
                        MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR,
                        MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                         MMU_CACHE_WB_WA),
                        MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                        (unsigned int*)pageTable
                       };
    /*
    ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given.
    */
    REGION regionOcmc = {
                         MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC,
                         MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                          MMU_CACHE_WB_WA),
                         MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                         (unsigned int*)pageTable
                        };

    /*
    ** Define Device Memory Region. The region between OCMC and DDR is
    ** configured as device memory, with R/W access in user/privileged modes.
    ** Also, the region is marked 'Execute Never'.
    */
    REGION regionDev = {
                        MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV,
                        MMU_MEMTYPE_STRONG_ORD_SHAREABLE,
                        MMU_REGION_NON_SECURE,
                        MMU_AP_PRV_RW_USR_RW  | MMU_SECTION_EXEC_NEVER,
                        (unsigned int*)pageTable
                       };

    /* Initialize the page table and MMU */
    MMUInit((unsigned int*)pageTable);

    /* Map the defined regions */
    MMUMemRegionMap(&regionDdr);
    MMUMemRegionMap(&regionOcmc);
    MMUMemRegionMap(&regionDev);

    /* Now Safe to enable MMU */
    MMUEnable((unsigned int*)pageTable);
}

With this configuration, the auto_mount will return error in the ff.c. While, when I disable the cache by comment out CacheEnable(CACHE_ALL);, it can work well.

For the device memory, I tried the MMU_MEMTYPE_STRONG_ORD_SHAREABLE, the same issue. and when tried MMU_MEMTYPE_DEVICE_NON_SHAREABLE, the uart, and SDIO will not work at all.

So could you help to check it, and give some comments on how to configure the cache.

Thanks!
Yaoming.

  

  • Hi Yaoming,

    Did you get this MMU init code from starterware ? SYS/BIOS has its own MMU module that manages the MMU. I am guessing that SYS/BIOS's MMU initialization code is conflicting with the MMU init code you have in your app. I would recommend replacing the above with SYS/BIOS MMU APIs.

    Please refer the SYS/BIOS MMU cdoc for more info on MMU APIs and some examples showing how to configure the MMU table: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_41_00_26/exports/bios_6_41_00_26/docs/cdoc/index.html#ti/sysbios/family/arm/a8/Mmu.html

    Let me know if the above change fixes the problem.

    Best,
    Ashish
  • Hi Ashish,

    Thanks for your comments!

    Here, I had a try in modifying the L1 cache policy for the normal memory(inner cache) to MMU_CACHE_WT_NOWA, the starterware can work now.

    So the cache policy for the device memory is OK. But the issue is in some buffer in the normal memory.

    I will continue to check the sysbios doc so as to configure the normal memory cache correctly.

    Thanks!
    Yaoming
  • Ashish Kapania said:
    Hi Yaoming,

    Did you get this MMU init code from starterware ? SYS/BIOS has its own MMU module that manages the MMU. I am guessing that SYS/BIOS's MMU initialization code is conflicting with the MMU init code you have in your app. I would recommend replacing the above with SYS/BIOS MMU APIs.

    Please refer the SYS/BIOS MMU cdoc for more info on MMU APIs and some examples showing how to configure the MMU table: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_41_00_26/exports/bios_6_41_00_26/docs/cdoc/index.html#ti/sysbios/family/arm/a8/Mmu.html

    Let me know if the above change fixes the problem.

    Best,
    Ashish

    Hi Ashish,

         For the SD card cache issue, I have made 2 test code:

      1. The test code based on the Starterware. I configured the MMU & Cache through the starterware code. After configuring the L1 cache to write through, it can work well.

      2. The test code based on the SYSBIOS application. Due to the test #1, I tried to configure the L1 cache to write through according to the SYSBIOS API doc. But I found that

           there is no configuration API to make DDR memory's attribute to L1 cache write back there.

      So could you give some comments on it?

    Thanks!

    Yaoming

  • Hi Yaoming,

    In order to mark a memory page as write-through cacheable, you will need to update that page's corresponding MMU entry. To change the cacheability of a page to outer and inner write-through no write-allocated, set the TEX[2:0] attribute for the page to 0, cacheable to true and bufferable to false. Here's some untested code showing how to do this using SYS/BIOS APIs:

    Mmu_FirstLevelDescAttrs attrs;
    Mmu_initDescAttrs(&attrs);
    
    attrs.type = Mmu_FirstLevelDescType_SECTION;
    attrs.tex = 0;
    attrs.cacheable = true;
    attrs.bufferable = false;
    
    /* Assuming we need set the attributes for memory page 0x82000000-0x82100000 with no translation */
    Mmu_setFirstLevelDesc((Ptr)0x82000000, (Ptr)0x82000000, &attrs);

    Best,

    Ashish

  • Hi Ashish,

    Thanks for your comments!
    I spent some time to verify it, and fix the SD card related issue in SYS BIOS.
    And I am continue my work for the M3/A8 mailbox communication.
    Again, I faced the issue in Cache, which I am not sure for it.

    So I have another post in e2e.ti.com/.../397826 .

    Could you please kindly check it and give me a hand there :)

    Thanks in advance !

    Yaoming