Hello,
We need to configure whole of L2 memory (as per the Corepac c66x datasheet max of 4MB) as SRAM.
Please find the platform.xdc file details below, here it is by default configured for l2mode as 0kB cache (we do not want L2 as cache) and we have modified the L2SRAM section for 4MB. However if we perform any simple math operation like multiplication of 2 arrays with size beyond 256k, the operation produces corrupt output. Earlier in this platform.xdc L2SRAM was configured for 256k. However if we restrict the buffers within 256k, the math operation goes fine.
We need to increase the size of L2 for max SRAM to accommodate all our application buffers( which are computation intensive). We will be later using DSPLIB & MATHLIB calls on these buffers. We have seen MATHLIB & DSPLIB giving pathetic performance if the memory is allocated in DDR.
Our assesment :Even though the L2 is configured as complete 4M SRAM in platform.xdc, we are not seeing its effect when we do operation beyond 256kB. Do we have to make this change elsewhere too ?
Please provide us details as to how we can canfigure L2 for 4MB SRAM.
***************************************************** platform.xdc ****************************************************************
/*!
* File generated by platform wizard. DO NOT MODIFY
*
*/
metaonly module Platform inherits xdc.platform.IPlatform {
config ti.platforms.generic.Platform.Instance CPU =
ti.platforms.generic.Platform.create("CPU", {
clockRate: 1000,
catalogName: "ti.catalog.c6000",
deviceName: "Vayu",
customMemoryMap:
[
["EXT_CODE",
{
name: "EXT_CODE",
base: 0x95000000,
len: 0x00200000, //0x00100000
space: "code/data",
access: "RWX",
}
],
["EXT_DATA",
{
name: "EXT_DATA",
base: 0x95200000, //0x95100000
len: 0x00800000, //0x00100000
space: "data",
access: "RW",
}
],
["EXT_HEAP",
{
name: "EXT_HEAP",
base: 0x95A00000, //0x95200000
len: 0x03200000, //0x03200000 0x00300000 50MB
space: "data",
access: "RW",
}
],
["TRACE_BUF",
{
name: "TRACE_BUF",
base: 0x9F000000,
len: 0x00060000,
space: "data",
access: "RW",
}
],
["EXC_DATA",
{
name: "EXC_DATA",
base: 0x9F060000,
len: 0x00010000,
space: "data",
access: "RW",
}
],
["PM_DATA",
{
name: "PM_DATA",
base: 0x9F070000,
len: 0x00020000,
space: "data",
access: "RWX",
}
],
["SR_0",
{
name: "SR_0",
base: 0xBFC00000,
len: 0x6400000,
space: "data",
access: "RWX",
}
],
["L2SRAM",
{
name: "L2SRAM",
base: 0x00800000,
len: 0x000400000,
space: "code/data",
access: "RWX",
}
],
],
l2Mode:"0k",
l1PMode:"32k",
l1DMode:"32k",
});
instance :
override config string codeMemory = "EXT_CODE";
override config string dataMemory = "EXT_DATA";
override config string stackMemory = "EXT_DATA";
}
Thanks,
Naveen Shetti
