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SSI Receive with DMA enabled.

Srinivasa Wunnimani
Intellectual 790 points
Other Parts Discussed in Thread: TM4C129ENCPDT

I have an application which reads data from SSI Receive FIFO via DMA.  Within fraction of a second of receiving the data from Master, the system crashes and there is a hard fault exception and I am unable to catch the cause of this exception using debugger. 

I have SYS/BIOS running on Tiva TM4C129 device.

Any clue towards this is appreciated.

  • TI__Mastermind 30830 points
    Which version of TI-RTOS are you using?
    Are you using the TI-RTOS SPI driver?
    Are you saying that when the fault occurs the debugger disconnects from the target and can't reconnect?
    Where have you programmed the DMA to write the incoming date to? Is it possible you've mistakenly configured it to write to Flash address space?

    Alan
  • in reply to Alan DeMars
    Intellectual 790 points

    Hi Alan,

    Thanks you for your quick response.

    1. Which version of TI-RTOS are you using?

    TI RTOS: 1_21_00_09.

    1. Are you using the TI-RTOS SPI driver?

    Yes.  I have attached the pseudo code, please find spiDMAError_code.c as attachment.

    1. Are you saying that when the fault occurs the debugger disconnects from the target and can't reconnect?

    The debugger is connected, I am able to stop the debugger, able to see the registers.  I am able to see the disassembly window and it just loops at address “000321d2” and never comes out of this.  Please find the screenshot file “spiDMAError_screenshot.png“ attached.

    1. Where have you programmed the DMA to write the incoming date to? Is it possible you've mistakenly configured it to write to Flash address space?

    I have programmed to read it to a variable DMABuffer, which is a global variable as below:

    MAP_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)(SSI0_BASE + SSI_O_DR), &DMABuffer[0][0], BUFFER_PAGE_SZ_WORDS);

    Regards

    Srinivasa

    1731.SPI_DMA_ERROR.ZIP

  • in reply to Srinivasa Wunnimani
    Intellectual 790 points
    Hi Alan,

    If my understanding is correct, the below function is called when we receive data on SPI using DMA. I have placed a break point in below function and was expecting to stop over here and debug.

    The hard fault exception occurred before control came to this ISR.


    /*
    * ======== SPITivaDMA_hwiFxn ========
    * ISR for the SPI when we use the DMA
    */
    static Void SPITivaDMA_hwiFxn (UArg arg)
    {
    SPI_Transaction *msg;
    SPITivaDMA_Object *object = ((SPI_Handle)arg)->object;
    SPITivaDMA_HWAttrs const *hwAttrs = ((SPI_Handle)arg)->hwAttrs;

    Log_print1(Diags_USER2, "SPI:(%p) interrupt context start",
    hwAttrs->baseAddr);

    #if !defined(MWARE)
    if (SSIMODE(hwAttrs->baseAddr)) {
    /* We know that at least the Tx channel triggered the interrupt */
    SSIIntDisable(hwAttrs->baseAddr, SSI_DMATX);
    }
    #endif

    I am trying to see DMASRCENDP, DMADSTENDP, and DMACHCTL in code composer studio debug registers, but I could not find them. As per datasheet these registers base address is mentioned as N/a.
    Can we see contents of these registers?
    Or
    Can we see value of register (without actually knowing the register name) using base address and offset address?

    Regards
    Srinivasa
  • in reply to Srinivasa Wunnimani
    TI__Mastermind 20480 points
    This ISR is called if you are using the TI-RTOS SPI driver (not by Tivaware's driverlib SSI driver). Transfers are initiated via a call to SPI_transfer(). You can see this with the _TI-RTOS_ SPI loopback example.

    I don't know why the uDMA registers aren't showing in the register view. Can you try the SPI loopback example and see if the registers show up in there?
  • in reply to Srinivasa Wunnimani
    TI__Mastermind 20480 points

    Also, I don't see DMAControlTable defined. Is it aligned to 1024.

  • in reply to Tom Kopriva
    Intellectual 790 points
    I have not initialized the DMAControl Tabled. Upon doing it, it is working fine.
    Thanks for pointing to me in the right direction.

    I will try the SPI loopback example and see if the registers show up in there.

    Regards
    Srinivasa
  • in reply to Srinivasa Wunnimani
    Intellectual 790 points

    In SPI loopback example also I am not seeing DMASRCENDP, DMADSTENDP, and DMACHCTL registers.

    Regards

    Srinivasa

  • in reply to Srinivasa Wunnimani
    TI__Mastermind 20480 points
    I'm not sure if the uDMA controller has those as dedicated registers.
    I think they are located in the uDMA control table and are also updated/modified by the uDMA controller (hence the alignment). Each entry is indexed to a specific uDMA channel. There are 4 words per channel and they line up to the registers you are looking for.
  • in reply to Tom Kopriva
    Intellectual 790 points

    Hi,

    I have configured SSI to get data from DMA.  The length of data that is available per frame from my peripheral may vary.   Sometime in one frame we may have two short integers (4 bytes) or we may even have up to 8 short integers (16 bytes).  During one scenario I am missing first two short integers and hence entire data is misaligned. 

    Case

    Number of short integers per frame

    Remarks

    1

    2

    Working Fine.

    2

    4

    Working Fine.

    3

    4

    Working Fine.

    4

    5

    Not Working.

    5

    8

    Working Fine.

    6

    8

    Working Fine.

    7

    8

    Working Fine.

     

    Working Fine means we are receiving all the data.

    Not working means two bytes from the first frame is missed out and hence alignment of all the next bytes received is misaligned.  This happens for only one case.

    I am using TI RTOS: 1_21_00_09 and I have attached pseudocode for reference.

    Is there anything that you can suggest from SSI or DMA configuration?

    Regards

    Srinivasa

     8030.spiDMA_pseudoCode.c

  • in reply to Srinivasa Wunnimani
    Intellectual 790 points
    Hi,

    Please ignore my previous question. Because of odd number few bytes are copied to next buffer.

    Regards
    Srinivasa
  • in reply to Srinivasa Wunnimani
    Intellectual 790 points
    Hi,

    I am very sorry, my question is still valid. By buffer size is 160 short int; it is defined as
    UWORD DMABuffer[2][160];

    I have two buffers of 160 for PING PONG operation.

    My data is of 5 short integers, so I should have 32 data points in one buffer. So I am missing data in first frame and hence subsequent frames are misaligned.

    Regards
    Srinivasa
  • in reply to Srinivasa Wunnimani
    Intellectual 790 points
    Hi,

    Sometimes I am missing data from SSI which is received via DMA. I have explained the problem scenario few days back and I have reviewed my code and I could not find issue with the code.

    Did you guys observe any similar problem in any of your projects?
    Microcontroller: Tiva tm4c129encpdt.

    Regards
    Srinivasa
  • in reply to Srinivasa Wunnimani
    TI__Mastermind 20480 points

    Srinivasa,

    I didn't see your post because this thread is already answered. It's not clear to me if this a issue related to the original post. Can you create a new post?