Hi,
I'm currently using SysBios (6.37.02.27) in SMP-mode on an ARM v7 processor. As in SMP-mode, two tasks (or one task and an ISR) actually run in parallel at the same time, the issue of memory model pops up when considering synchronization between two concurrent control flows (two tasks or task/ISR) . As ARM v7 has a very relaxed memory model [2], explicit ordering instructions ("dmb", or "sync") are required [3] in order to guarantee correctness. There are tons of literature about this topic [1], [3], [4], both from academia and practical engineering (notably the Linux Kernel).
However, the SysBios manual does not state ANYTHING about this topic. For example, does the use of a Semaphore include the necessary memory barriers? How about the Event module? Does the following example work?
int global_var_result = 0;
void tasks1(...)
{
/* produces result */
[...]
/* store result */
global_var_result = ...;
/* Set event for task2, see below */
Event_post(...);
[...]
}
void task2(...)
{
Event_Wait(...)
/* read result */
.. = global_var_result;
}
or does it have to be changed to
void tasks1(...)
{
/* produces result */
[...]
/* store result */
global_var_result = ...;
smp_wmb(); // <- enforce write ordering!
/* Set event for task2, see below */
Event_post(...);
[...]
}
void task2(...)
{
Event_Wait(...)
smp_rmb(); // <- enforce read ordering!
/* read result */
.. = global_var_result;
}
Note: The smp_wmb() and smp_rmb() are the names used in the Linux Kernel.
My questions are:
1. What guarantees are included in the following SysBios synchronization primitives: Semaphore, Mutex, Gate* (all Gate-Type APIs), Event?
2. What guarantees are not included in the following SysBios synchronization primitives: Semaphore, Mutex, Gate* (all Gate-Type APIs), Event?
3. Are there any built-in SysBios primitives (like "smp_rmb" in Linux Kernel) that can be used or do I have to code this in assembly language myself?
4. Is there something similar to the "spinlock" primitive in the Linux-Kernel that enables mutual exclusion between both tasks and ISRs? If not how can this be achieved in SMP-enabled SysBios?
Thanks for your answers. Best Regards,
Matthias
[1] http://www.cl.cam.ac.uk/~pes20/weakmemory/#PA
[2] http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf
[4] preshing.com/.../memory-barriers-are-like-source-control-operations
