Hi Sir,
In our design , we're using two GPIOs(GPIO6[2], GPIO6[10]) of the same bank(GPIO bank6) as two interrupt sources.
At the entrance of GPIO's ISR, to avoid missing a new coming interrupt, we disable the GPIO bank6 in the Interrupt Pre-Bank Enable Register.
The C code is given as following:
void GpioBank6Isr(void)
{
Uint32 IntStatusRegVal;
GPIOBankIntDisable(SOC_GPIO_0_REGS, 6); //Disable the bank 6 in the Interrupt Pre-bank Enable Register
IntStatusRegVal = GetBankIntStatusReg(6);
IntSystemStatusClear(SYS_INT_GPIOB6);
if (IntStatusRegVal&((Uint32)(1)<<2))
{
GPIO6_2Isr();
}
if(IntStatusRegVal&((Uint32)(1)<<10))
{
GPIO6_10Isr();
}
GPIOBankIntEnable(SOC_GPIO_0_REGS, 6); //Enable the bank 6 in the Interrupt Pre-bank Enable Register
}
When the GPIO6[10] interrupt is processed through this GpioBank6Isr, if a new GPIO6[2] interrupt occurs after the
statement "GPIOBankIntDisable(SOC_GPIO_0_REGS, 6);", the new interrupt will be missed because the GPIO6[2] bit in the Interrupt
Status Register isn't set.
It seems that the Interrupt Pre-Bank Enable Register is also used to gate the Raw Interrupt Status Register of GPIOs.
Is it a design issue of AM1806 or not?
Thanks,
Leo
